CS4297A
CS4297A
ary audio codecs. Both input and output AC-link
audio frames are organized as a sequence of 256 se-
rial bits forming 13 groups referred to as ‘slots’.
During each audio frame, data is passed bi-direc-
tionally between the CS4297A and the controller.
The input frame is driven from the CS4297A on the
SDATA_IN line. The output frame is driven from
the controller on the SDATA_OUT line. The con-
troller is also responsible for issuing reset com-
mands via the RESET# signal. Following a Cold
Reset, the CS4297A is responsible for notifying the
controller that it is ready for operation after syn-
chronizing its internal functions. The CS4297A
AC-link signals must use the same digital supply
voltage as the controller chip, either +5 V or
+3.3 V. See Section 3, AC Link Frame Definition,
for detailed AC-link information.
2. GENERAL DESCRIPTION
The CS4297A is a mixed-signal serial audio Codec
compliant to the Intel® Audio Codec ‘97 Specifica-
tion, revision 2.1 [1]. It is designed to be paired
with a digital controller, typically located on the
PCI bus or integrated within the system core logic
chip set. The controller is responsible for all com-
munications between the CS4297A and the remain-
der of the system. The CS4297A contains two
distinct functional sections: digital and analog. The
digital section includes the AC-link interface,
S/PDIF interface, serial data port, and power man-
agement support. The analog section includes the
analog input multiplexer (mux), stereo output mix-
er, mono output mixer, stereo Analog-to-Digital
Converters (ADCs), stereo Digital-to-Analog Con-
verters (DACs), and their associated volume con-
trols.
2.2
Control registers
2.1
AC-Link
The CS4297A contains a set of AC ’97 compliant
All communication with the CS4297A is estab- control registers and a set of Cirrus Logic defined
lished with a 5-wire digital interface to the control- control registers. These registers control the basic
ler, as shown in Figure 7. This interface is called functions and features of the CS4297A. Read ac-
the AC-link. All clocking for the serial communi-
cation is synchronous to the BIT_CLK signal.
BIT_CLK is generated by the primary audio codec
cesses of the control registers by the AC ’97 con-
troller are accomplished with the requested register
index in Slot 1 of a SDATA_OUT frame. The fol-
and is used to clock the controller and any second- lowing SDATA_IN frame will contain the read
Digital AC’97
Controller
CODEC
SYNC
BIT_CLK
SDATA_OUT
SDATA_IN
RESET#
Figure 7. AC-link Connections
10
10
DS318PP6
CIRRUS [ CIRRUS LOGIC ]
