5.6
AUX Port Digital Interface Formats
These serial data lines are used when supporting the TDM Mode of operation with an external ADC or
S/PDIF receiver attached. The AUX serial port operates only as a clock master. The AUX_SCLK will op-
erate at 64xFs, where Fs is equal to the ADC sample rate (FS on the TDM interface). If the AUX_SDIN
signal is not being used, it should be tied to AGND via a pull-down resistor.
Hardware Mode
The AUX port will only operate in the Left Justified digital interface format and supports bit depths ranging
from 16 to 24 bits (see figure 16 on page 35 for timing relationship between AUX_LRCK and AUX_SCLK).
Software Mode
The AUX port will operate in either the Left Justified or I²S digital interface format with bit depths ranging
from 16 to 24 bits. Settings for the AUX port are made through the register “Miscellaneous Control (ad-
dress 04h)” on page 44.
5.6.1 I²S
AUX_LRCK
Left Channel
Right Channel
AUX_SCLK
AUX_SDIN
M SB
LSB
M SB
LS B
MSB
AUX2
AUX1
Figure 15. AUX I²S Format
5.6.2 Left Justified
AUX_LRCK
Left Channel
Right Channel
AUX_SCLK
AUX_SDIN
M SB
LSB
M SB
LSB
MSB
AUX2
AUX1
Figure 16. AUX Left Justified Format
DS646PP2
35
CIRRUS [ CIRRUS LOGIC ]
