FS is sampled as valid on the rising SCLK edge preceding the most significant bit of the first data
sample and must be held valid for at least 1 SCLK period.
NOTE: The ADC does not meet the timing requirements for proper operation in Quad-Speed
Mode.
256 clks
Bit or Word Wide
FS
SCLK
MSB
LSB
LSB MSB
MSB
LSB MSB
LSB MSB
LSB MSB
AOUT2
LSB MSB
AOUT3
LSB MSB
LSB MSB
LSB MSB
LSB MSB
LSB MSB
LSB MSB
LSB MSB
LSB MSB
DAC_SDIN
AOUT1
32 clks
AOUT4
32 clks
AOUT5
32 clks
AOUT6
32 clks
AOUT7
32 clks
AOUT8
32 clks
32 clks
32 clks
LSB MSB
LSB MSB
LSB MSB
ADC_SDOUT
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AUX1
AUX2
32 clks
32 clks
32 clks
32 clks
32 clks
32 clks
32 clks
32 clks
Figure 14. TDM Serial Audio Format
5.5.2 I/O Channel Allocation
Digital
Input/Output
Interface
Format
Analog Output/Input Channel Allocation
from/to Digital I/O
DAC_SDIN
TDM
TDM
Table 6. Serial Audio Interface Channel Allocations
AOUT 1,2,3,4,5,6,7,8
ADC_SDOUT
AIN 1,2,3,4,5,6; (2 additional channels from AUX_SDIN)
34
DS646PP2
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