CS42435
No Power
1. VQ = ?
2. Aout bias = ?
3. No audio signal
generated.
Power-Down
1. VQ discharge to 0 V.
2. Aout bias = Hi-Z.
3. No audio signal generated.
4. Control Port Registers retain
settings.
Yes
PDN bit = '1'b?
No
Power-Down (Power Applied)
1. VQ = 0 V.
2. Aout = HI-Z.
3. No audio signal generated.
4. Control Port Registers reset
to default.
Power-Up
1. VQ = VA/2.
2. Aout bias = VQ.
Yes
RST = Low?
No
Control Port
Accessed
Sub-Clocks Applied
1. LRCK valid.
2. SCLK valid.
3. Audio samples
processed.
Control Port
No
Yes
Access Detected?
No
Valid
MCLK/LRCK
Ratio?
Hardware Mode
H/W pins setup to
desired settings.
Software Mode
Registers setup to
desired settings.
Yes
No
No
Valid MCLK
Applied?
Valid MCLK
Applied?
2000 LRCK delay
Yes
Yes
PDN bit set
to '1'b
RST = Low
Normal Operation
1. VQ = VA/2.
2. Aout bias = VA/2.
3. Audio signal generated per register settings.
ERROR: Power removed
ERROR: MCLK/LRCK ratio change
ERROR: MCLK removed
Analog Output Mute
Analog Output Freeze
1. VQ = VA/2.
1. VQ = VA/2.
2. Aout bias = VA/2.
3. No audio signal generated.
2. Aout bias = VA/2 + last audio sample.
3. No audio signal generated.
Figure 10. Audio Output Initialization Flow Chart
30
DS685F1
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