CS42435
5. APPLICATIONS
5.1
Overview
The CS42435 is a highly integrated mixed signal 24-bit audio CODEC comprised of 4 analog-to-digital con-
verters (ADC) implemented using multi-bit delta-sigma techniques and 8 digital-to-analog converters (DAC)
also implemented using multi-bit delta-sigma techniques.
Other functions integrated within the CODEC include independent digital volume controls for each DAC, dig-
ital de-emphasis filters for the DAC, digital volume control with gain on each ADC channel, ADC high-pass
filters, and an on-chip voltage reference.
The serial audio interface ports allow up to 8 DAC channels and 6 ADC channels in a Time-Division Multi-
plexed (TDM) interface format. The CS42435 features an Auxiliary Port used to accommodate an additional
two channels of PCM data on the ADC_SDOUT data line in the TDM digital interface format. See “AUX Port
Digital Interface Formats” on page 33 for details.
The CS42435 operates in one of three oversampling modes based on the input sample rate. Mode selection
is determined automatically based on the MCLK frequency setting. Single-Speed Mode (SSM) supports in-
put sample rates up to 50 kHz and uses a 128x oversampling ratio. Double-Speed Mode (DSM) supports
input sample rates up to 100 kHz and uses an oversampling ratio of 64x. Quad-Speed Mode (QSM) sup-
ports input sample rates up to 200 kHz and uses an oversampling ratio of 32x (Note: QSM for the ADC is
only supported in the I²S, Left-Justified, Right-Justified interface formats. QSM is not supported for the ADC
in the TDM interface format). Note: QSM is only available in Software Mode (see “System Clocking” on
page 32 for details).
All functions can be configured through software via a serial control port operable in SPI Mode or in I²C
Mode. A Hardware, Stand-Alone Mode is also available, allowing configuration of the CODEC on a more
limited basis. See Table 2 for the default configuration in Hardware Mode.
Figure 1 on page 11 and Figure 2 on page 12 show the recommended connections for the CS42435 in
Software and Hardware Mode, respectively. See “Register Description” on page 40 for the default register
settings and options in Software Mode.
Hardware Mode Feature Summary
Function
Default Configuration
All ADC’s are enabled
All DAC’s are enabled
Device is powered up
Hardware Control
Note
Power Down ADC
Power Down DAC
Power Down Device
-
-
-
-
-
-
Selectable between 256Fs and
512Fs
MCLK Frequency Select
“MFREQ” pin 3
see Section 5.4
Freeze Control
N/A
-
-
-
-
AUX Serial Port Interface Format
Left-Justified
High Pass Filter is always
enabled
ADC1 High Pass Filter Freeze
-
-
DAC De-Emphasis
No De-Emphasis applied
Disabled
-
-
-
-
ADC1 Single-Ended Mode
All DAC Volume = 0 dB, un-
muted, not inverted
DAC Volume Control/Mute/Invert
-
-
ADC Volume Control
All ADC Volume = 0 dB
Immediate Change
Immediate Change
-
-
-
-
-
-
DAC Soft Ramp/Zero Cross
ADC Soft Ramp/Zero Cross
Table 2. Hardware Configurable Settings
DS685F1
27
CIRRUS [ CIRRUS LOGIC ]
