CS42435
SWITCHING SPECIFICATIONS - CONTROL PORT - I²C MODE
(VLC = 1.8 V - 5.0 V, VLS = VD = 3.3 V, VA = 5.0 V; Inputs: Logic 0 = DGND, Logic 1 = VLC, SDA C = 30 pF)
L
Parameter
Symbol
Min
Max
Unit
SCL Clock Frequency
f
-
100
kHz
scl
RST Rising Edge to Start
t
500
4.7
4.0
4.7
4.0
4.7
0
-
ns
µs
µs
µs
µs
µs
µs
ns
µs
ns
µs
ns
irs
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low time
t
-
buf
t
-
hdst
t
-
low
Clock High Time
t
-
high
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling
SDA Setup time to SCL Rising
Rise Time of SCL and SDA
t
-
sust
(Note 20)
t
-
hdd
t
250
-
-
1
sud
(Note 21)
(Note 21)
t
rc
Fall Time SCL and SDA
t
-
300
-
fc
Setup Time for Stop Condition
Acknowledge Delay from SCL Falling
t
4.7
300
susp
t
1000
ack
Notes:
20. Data must be held for sufficient time to bridge the transition time, t , of SCL.
fc
21. Guaranteed by design.
RST
t
irs
Repeated
Start
Stop
Start
Stop
t
t
rd
fd
SDA
SCL
t
t
t
t
t
buf
t
high
hdst
fc
susp
hdst
low
t
t
t
t
t
t
sust
sud
ack
rc
hdd
Figure 7. Control Port Timing - I²C Format
DS685F1
23
CIRRUS [ CIRRUS LOGIC ]
