CS42426
Send start condition.
Send 10011xx1(chip address & read operation).
Receive acknowledge bit.
Receive byte, contents of selected register.
Send acknowledge bit.
Send stop condition.
Setting the auto increment bit in the MAP allows successive reads or writes of consecutive registers. Each
byte is separated by an acknowledge bit.
4.7
Interrupts
The CS42426 has a comprehensive interrupt capability. The INT output pin is intended to drive the interrupt
input pin on the host microcontroller. The INT pin may be set to be active low, active high or active low with
no active pull-up transistor. This last mode is used for active low, wired-OR hook-ups, with multiple periph-
erals connected to the microcontroller interrupt input pin.
Many conditions can cause an interrupt, as listed in the interrupt status register descriptions (see “Interrupt
Status (address 20h) (Read Only)” on page 56). Each source may be masked off through mask register bits.
In addition, each source may be set to rising edge, falling edge, or level-sensitive. Combined with the option
of level-sensitive or edge-sensitive modes within the microcontroller, many different configurations are pos-
sible, depending on the needs of the equipment designer.
4.8
Reset and Power-Up
Reliable power-up can be accomplished by keeping the device in reset until the power supplies, clocks and
configuration pins are stable. It is also recommended that reset be activated if the analog or digital supplies
drop below the recommended operating condition to prevent power-glitch-related issues.
When RST is low, the CS42426 enters a low-power mode and all internal states are reset, including the
control port and registers, and the outputs are muted. When RST is high, the control port becomes opera-
tional, and the desired settings should be loaded into the control registers. Writing a 0 to the PDN bit in the
Power Control Register will then cause the part to leave the low-power state and begin operation. If the in-
ternal PLL is selected as the clock source, the serial audio outputs will be enabled after the PLL has settled
(see “Power Control (address 02h)” on page 43 for more details).
The delta-sigma modulators settle in a matter of microseconds after the analog section is powered, either
through the application of power or by setting the RST pin high. However, the voltage reference will take
much longer to reach a final value due to the presence of external capacitance on the FILT+ pin. A time
delay of approximately 80 ms is required after applying power to the device or after exiting a reset state.
During this voltage reference ramp delay, all serial ports and DAC outputs will be automatically muted.
DS604F1
37
CIRRUS [ CIRRUS LOGIC ]
