CS42426
4.5.4.3 OLM Config #3
This configuration will support up to 6 channels of DAC data and 6 channels of ADC data. OLM Config #3
will handle up to 20-bit ADC samples at an Fs of 48 kHz and 24-bit DAC samples at an Fs of 48 kHz. Since
the ADC’s data stream is configured to use the ADC_SDOUT output and the internal and external ADCs
are clocked from the ADC_SP, the sample rate for the DAC Serial Port can be different from the sample
rate of the ADC serial port.
Register / Bit Settings
Functional Mode Register (addr = 03h)
Set DAC_FMx = 00,01,10
Description
DAC_LRCK can run at SSM, DSM, or QSM independent of ADC_LRCK
ADC_LRCK can run at SSM, DSM, or QSM independent of DAC_LRCK
Configure ADC_SDOUT to be clocked from the ADC_SP clocks.
Set ADC_FMx = 00,01,10
Set ADC_CLK_SEL = 1
Interface Format Register (addr = 04h)
Set DIFx bits to proper serial format
Set ADC_OLx bits = 00,01
Select the digital interface format when not in One-Line Mode
Select ADC operating mode, see table below for valid combinations
Select DAC operating mode, see table below for valid combinations
Set DAC_OLx bits = 00,01,10
Misc. Control Register (addr = 05h)
Set DAC_SP M/S = 1
Set DAC Serial Port to Master Mode.
Set ADC Serial Port to Master Mode or Slave Mode.
Identify external ADC clock source as ADC Serial Port.
Set ADC_SP M/S = 0 or 1
Set EXT ADC SCLK = 0
DAC Mode
Not One-Line Mode
DAC_SCLK=64Fs
Not One- DAC_LRCK=SSM/DSM/QSM DAC_LRCK=SSM/DSM
Line Mode ADC_SCLK=64Fs ADC_SCLK=64Fs
One-Line Mode #1
One-Line Mode #2
DAC_SCLK=256Fs
DAC_LRCK=SSM
ADC_SCLK=64Fs
DAC_SCLK=128Fs
ADC_LRCK=SSM/DSM/QSM ADC_LRCK=SSM/DSM/QSM ADC_LRCK=SSM/DSM/QSM
DAC_SCLK=64Fs
One-Line DAC_LRCK=SSM/DSM/QSM DAC_LRCK=SSM/DSM
Mode #1 ADC_SCLK=128Fs
DAC_SCLK=128Fs
DAC_SCLK=256Fs
DAC_LRCK=SSM
ADC_SCLK=128Fs
ADC_LRCK=SSM
ADC Mode
ADC_SCLK=128Fs
ADC_LRCK=SSM
ADC_LRCK=SSM
One-Line
not valid
Mode #2
not valid
not valid
MCLK
64Fs,128Fs
SCLK_PORT1
LRCK
SCLK
ADC_SCLK
LRCK_PORT1
SDIN_PORT1
ADC_LRCK
MCLK
RMCK
ADC_SDOUT
SDOUT1
SDOUT2
ADCIN1
ADCIN2
CS5361
CS5361
64Fs,128Fs,256Fs
DAC_SCLK
SCLK_PORT2
LRCK_PORT2
DAC_LRCK
SDOUT1_PORT2
SDOUT2_PORT2
SDOUT3_PORT2
DAC_SDIN1
DAC_SDIN2
DAC_SDIN3
DIGITAL AUDIO
PROCESSOR
CS42426
Figure 19. OLM Configuration #3
DS604F1
33
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