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CS42426-DQZR 参数 Datasheet PDF下载

CS42426-DQZR图片预览
型号: CS42426-DQZR
PDF下载: 下载PDF文件 查看货源
内容描述: 114分贝192千赫6声道编解码器PLL [114 dB, 192 kHz 6-Ch Codec with PLL]
分类和应用: 解码器编解码器消费电路商用集成电路
文件页数/大小: 73 页 / 1381 K
品牌: CIRRUS [ CIRRUS LOGIC ]
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CS42426  
4.5.4.4 OLM Config #4  
This One-Line Mode configuration can support up to 6 channels of DAC data on 2 DAC_SDIN pins and 2  
channels of ADC data and will handle up to 24-bit samples at a sampling frequency of 48 kHz on all chan-  
nels for both the DAC and ADC. The output data stream of the internal ADCs can be configured to run at  
the DAC_SP clock speeds or to run at the ADC_SP rate. The DAC_SP and ADC_SP can operate at differ-  
ent Fs rates.  
Register / Bit Settings  
Description  
Functional Mode Register (addr = 03h)  
Set DAC_FMx = 00,01,10  
DAC_LRCK can run at SSM, DSM, or QSM independent of ADC_LRCK  
ADC_LRCK can run at SSM, DSM, or QSM independent of DAC_LRCK  
Set ADC_FMx = 00,01,10  
Configure ADC_SDOUT to be clocked from the ADC_SP or DAC_SP  
clocks.  
Set ADC_CLK_SEL = 0 or 1  
Interface Format Register (addr = 04h)  
Set DIFx bits to proper serial format  
Select the digital interface format when not in One-Line Mode  
Set ADC operating mode to Not One-Line Mode since only 2 channels of  
ADC are supported  
Set ADC_OLx bits = 00  
Set DAC_OLx bits = 00,01,10  
Select DAC operating mode, see table below for valid combinations  
Misc. Control Register (addr = 05h)  
Set DAC_SP M/S = 0 or 1  
Set DAC Serial Port to Master Mode or Slave Mode.  
Set ADC Serial Port to Master Mode or Slave Mode.  
External ADCs are not used. Leave bit in default state.  
Set ADC_SP M/S = 0 or 1  
Set EXT ADC SCLK = 0  
DAC Mode  
Not One-Line Mode  
DAC_SCLK=64Fs/128Fs  
Not One- DAC_LRCK=SSM/DSM/QSM DAC_LRCK=SSM/DSM  
Line Mode ADC_SCLK=64Fs/128Fs ADC_SCLK=64Fs/128Fs  
One-Line Mode #1  
One-Line Mode #2  
DAC_SCLK=256Fs  
DAC_LRCK=SSM  
DAC_SCLK=128Fs  
ADC_SCLK=64Fs/128Fs  
ADC_LRCK=SSM/DSM/QSM ADC_LRCK=SSM/DSM/QSM ADC_LRCK=SSM/DSM/QSM  
ADC Mode  
One-Line  
Mode #1  
not valid  
not valid  
not valid  
not valid  
not valid  
not valid  
One-Line  
Mode #2  
MCLK  
64Fs,128Fs  
SCLK_PORT1  
ADC_SCLK  
ADC_LRCK  
ADC_SDOUT  
LRCK_PORT1  
SDIN_PORT1  
RMCK  
ADCIN1  
ADCIN2  
SDIN_PORT2  
64Fs,128Fs, 256Fs  
SCLK_PORT2  
DAC_SCLK  
LRCK_PORT2  
DAC_LRCK  
DAC_SDIN1  
DAC_SDIN2  
SDOUT1_PORT2  
SDOUT2_PORT2  
SDOUT3_PORT2  
DAC_SDIN3  
DIGITAL AUDIO  
PROCESSOR  
CS42426  
Figure 20. OLM Configuration #4  
34  
DS604F1