CS42416
6.10.3 AUTO-MUTE (AMUTE)
Default = 1
0 - Disabled
1 - Enabled
Function:
The digital-to-analog converters of the CS42416 will mute the output following the reception of 8192
consecutive audio samples of static 0 or -1. A single sample of non-static data will release the mute.
Detection and muting is done independently for each channel. The quiescent voltage on the output
will be retained, and the MUTEC pin will go active during the mute period. The muting function is af-
fected, similar to volume control changes, by the Soft and Zero Cross bits (SZC[1:0]).
6.10.4 SOFT VOLUME RAMP-UP AFTER ERROR (RMP_UP)
Default = 0
0 - Disabled
1 - Enabled
Function:
An un-mute will be performed after executing a filter mode change, after a MCLK/LRCK ratio change
or error, and after changing the Functional Mode. When this feature is enabled, this un-mute is affect-
ed, similar to attenuation changes, by the Soft and Zero Cross bits (SZC[1:0]). When disabled, an
immediate un-mute is performed in these instances.
Note: For best results, it is recommended that this bit be used in conjunction with the RMP_DN bit.
6.10.5 SOFT RAMP-DOWN BEFORE FILTER MODE CHANGE (RMP_DN)
Default = 0
0 - Disabled
1 - Enabled
Function:
A mute will be performed prior to executing a filter mode or de-emphasis mode change. When this
feature is enabled, this mute is affected, similar to attenuation changes, by the Soft and Zero Cross
bits (SZC[1:0]). When disabled, an immediate mute is performed prior to executing a filter mode or
de-emphasis mode change.
Note: For best results, it is recommended that this bit be used in conjunction with the RMP_UP bit.
6.11 Channel Mute (address 0Eh)
7
6
5
4
3
2
1
0
Reserved
Reserved
B3_MUTE
A3_MUTE
B2_MUTE
A2_MUTE
B1_MUTE
A1_MUTE
6.11.1 INDEPENDENT CHANNEL MUTE (XX_MUTE)
Default = 0
0 - Disabled
1 - Enabled
Function:
The digital-to-analog converter outputs of the CS42416 will mute when enabled. The quiescent volt-
age on the outputs will be retained. The muting function is affected, similar to attenuation changes,
by the Soft and Zero Cross bits (SZC[1:0]).
52
DS602F1
CIRRUS [ CIRRUS LOGIC ]
