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CS42416_05 参数 Datasheet PDF下载

CS42416_05图片预览
型号: CS42416_05
PDF下载: 下载PDF文件 查看货源
内容描述: 110分贝192千赫6声道编解码器PLL [110 dB, 192 kHz 6-Ch Codec with PLL]
分类和应用: 解码器编解码器
文件页数/大小: 73 页 / 1386 K
品牌: CIRRUS [ CIRRUS LOGIC ]
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CS42416  
6.17.2 DE-EMPHASIS SELECT BITS (DE-EMPHX)  
Default = 00  
00 - Reserved  
01 - De-Emphasis for 32 kHz sample rate.  
10 - De-Emphasis for 44.1 kHz sample rate.  
11 - De-Emphasis for 48 kHz sample rate.  
Function:  
Used to specify which de-emphasis filter to apply when the “Force PLL Lock (FRC_PLL_LK)” on  
page 49 is enabled.  
6.17.3 INTERRUPT PIN CONTROL (INTX)  
Default = 00  
00 - Active high; high output indicates interrupt condition has occurred  
01 - Active low; low output indicates an interrupt condition has occurred  
10 - Open drain, active low. Requires an external pull-up resistor on the INT pin.  
11 - Reserved  
Function:  
Determines how the interrupt pin (INT) will indicate an interrupt condition.  
6.18 Interrupt Status (address 20h) (Read Only)  
7
6
5
4
3
2
1
0
UNLOCK  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
OverFlow  
Reserved  
For all bits in this register, a “1” means the associated interrupt condition has occurred at least once since the reg-  
ister was last read. A ”0” means the associated interrupt condition has NOT occurred since the last reading of the  
register. Reading the register resets all bits to 0. Status bits that are masked off in the associated mask register will  
always be “0” in this register.  
6.18.1 PLL UNLOCK (UNLOCK)  
Default = 0  
Function:  
PLL unlock status bit. This bit will go high if the PLL becomes unlocked.  
6.18.2 ADC OVERFLOW (OVERFLOW)  
Default = 0  
Function:  
Indicates that there is an over-range condition anywhere in the CS42416 ADC signal path.  
56  
DS602F1