CS2100-CP
8.5
Ratio (Address 06h - 09h)
7
6
5
4
3
2
1
0
MSB
MSB-8
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...................................................................................................................................................
...................................................................................................................................................
...................................................................................................................................................
MSB-7
MSB-15
LSB+8
LSB
LSB+15
LSB+7
These registers contain the User Defined Ratio as shown in the “Register Quick Reference” section on
page 24. These 4 registers form a single 32-bit ratio value as shown above. See “Output to Input Frequency
Ratio Configuration” on page 16 and “Calculating the User Defined Ratio” on page 30 for more details.
8.6
Function Configuration 1 (Address 16h)
7
6
5
4
3
2
1
0
ClkSkipEn
AuxLockCfg
Reserved
RefClkDiv1
RefClkDiv0
Reserved
Reserved
Reserved
8.6.1
Clock Skip Enable (ClkSkipEn)
This bit enables clock skipping mode for the PLL and allows the PLL to maintain lock even when the
CLK_IN has missing pulses.
ClkSkipEn
PLL Clock Skipping Mode
Disabled.
0
1
Enabled.
Application:
“CLK_IN Skipping Mode” on page 13
Note:
f
must be < 80 kHz to use this feature.
CLK_IN
8.6.2
AUX PLL Lock Output Configuration (AuxLockCfg)
When the AUX_OUT pin is configured as a lock indicator (AuxOutSrc[1:0] = 11), this bit configures the
AUX_OUT driver to either push-pull or open drain. It also determines the polarity of the lock signal. If
AUX_OUT is configured as a clock output, the state of this bit is disregarded.
AuxLockCfg
AUX_OUT Driver Configuration
0
Push-Pull, Active High (output ‘high’ for unlocked condition, ‘low’ for locked condition).
Open Drain, Active Low (output ‘low’ for unlocked condition, high-Z for locked condition).
“Auxiliary Output” on page 20
1
Application:
Note: AUX_OUT is an unlock indicator, signalling an error condition when the PLL is unlocked. There-
fore, the pin polarity is defined relative to the unlock condition.
8.6.3
Reference Clock Input Divider (RefClkDiv[1:0])
Selects the input divider for the timing reference clock.
RefClkDiv[1:0]
Reference Clock Input Divider
REF_CLK Frequency Range
32 MHz to 75 MHz (50 MHz with XTI)
16 MHz to 37.5 MHz
00
÷ 4.
01
÷ 2.
10
÷ 1.
8 MHz to 18.75 MHz
11
Reserved.
Application:
“Internal Timing Reference Clock Divider” on page 12
28
DS840PP1
CIRRUS [ CIRRUS LOGIC ]
