CS2100-CP
8. REGISTER DESCRIPTIONS
In I²C Mode all registers are read/write unless otherwise stated. In SPI mode all registers are write only. All “Re-
served” registers must maintain their default state to ensure proper functional operation. The default state of each
bit after a power-up sequence or reset is indicated by the shaded row in the bit decode table and in the “Register
Quick Reference” on page 24.
Control port mode is entered when the device recognizes a valid chip address input on its I²C/SPI serial control pins
and the EnDevCfg1 and EnDevCfg2 bits are set to 1.
8.1
Device I.D. and Revision (Address 01h)
7
6
5
4
3
2
1
0
Device4
Device3
Device2
Device1
Device0
Revision2
Revision1
Revision0
8.1.1
8.1.2
8.2
Device Identification (Device[4:0]) - Read Only
I.D. code for the CS2100.
Device[4:0]
Device
00000
CS2100.
Device Revision (Revision[2:0]) - Read Only
CS2100 revision level.
REVID[2:0]
Revision Level
100
B2.
Device Control (Address 02h)
7
6
5
4
3
2
1
0
Unlock
FsDet1
FsDet0
Reserved
AutoRMod
Reserved
AuxOutDis
ClkOutDis
8.2.1
Unlock Indicator (Unlock) - Read Only
Indicates the lock state of the PLL.
Unlock
PLL Lock State
PLL is Locked.
PLL is Unlocked.
0
1
8.2.2
PLL Input Sample Rate Indicator (FsDet[1:0]) - Read Only
Indicates the range of the frequency of CLK_IN relative to the frequency of SysClk. For audio applications,
this can be used to distinguish single-, double-, and quad-speed modes.
fSysClk / fCLK_IN
FsDet[1:0]
00
> 224.
01
96 to 224.
10
< 96.
11
Reserved.
Application:
“CLK_IN Frequency Detector” on page 13
DS840PP1
25
CIRRUS [ CIRRUS LOGIC ]
