CS2100-CP
8.3.2
Auxiliary Output Source Selection (AuxOutSrc[1:0])
Selects the source of the AUX_OUT signal.
AuxOutSrc[1:0]
Auxiliary Output Source
RefClk.
00
01
CLK_IN.
10
CLK_OUT.
11
PLL Lock Status Indicator.
“Auxiliary Output” on page 20
Application:
Note: When set to 11, AuxLckCfg sets the polarity and driver type (“AUX PLL Lock Output Configura-
tion (AuxLockCfg)” on page 28).
8.3.3
Enable Device Configuration Registers 1 (EnDevCfg1)
This bit, in conjunction with EnDevCfg2, enables control port mode. Both bits must be set to 1 during ini-
tialization.
EnDevCfg1
Register State
0
Disabled.
1
Enabled.
Application:
“SPI / I²C Control Port” on page 22
Note: EnDevCfg2 must also be set to enable control port mode (“SPI / I²C Control Port” on page 22).
8.4
Global Configuration (Address 05h)
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
Reserved
Freeze
Reserved
Reserved
EnDevCfg2
8.4.1
Device Configuration Freeze (Freeze)
Setting this bit allows writes to the Device Control and Device Configuration registers (address 02h - 04h)
but keeps them from taking effect until this bit is cleared.
FREEZE
Device Control and Configuration Registers
0
Register changes take effect immediately.
Modifications may be made to Device Control and Device Configuration registers (registers 02h-04h) without
the changes taking effect until after the FREEZE bit is cleared.
1
8.4.2
Enable Device Configuration Registers 2 (EnDevCfg2)
This bit, in conjunction with EnDevCfg1, enables control port mode. Both bits must be set to 1 during ini-
tialization.
EnDevCfg2
Register State
0
Disabled.
1
Enabled.
Application:
“SPI / I²C Control Port” on page 22
Note: EnDevCfg1 must also be set to enable control port mode (“SPI / I²C Control Port” on page 22).
DS840PP1
27
CIRRUS [ CIRRUS LOGIC ]
