CS2000-OTP
6.3.5
Low-Frequency Ratio Configuration (LFRatioCfg)
Determines how to interpret the currently indexed 32-bit User Defined Ratio when the dynamic ratio based
Hybrid PLL Mode is selected (either manually or automatically, see section 5.4.6 on page 16).
LFRatioCfg
Ratio Bit Encoding Interpretation when Input Clock Source is CLK_IN
20.12 - High Multiplier.
0
1
12.20 - High Accuracy.
Application:
“User Defined Ratio (RUD), Frequency Synthesizer Mode” on page 14
Note: When the static ratio based Frequency Synthesizer Mode is selected (either manually or auto-
matically), the currently indexed User Defined Ratio will always be interpreted as a 12.20 fixed point value,
regardless of how this parameter is set.
6.3.6
M2 Pin Configuration (M2Config[2:0])
Controls which special function is mapped to the M2 pin.
M2Config[2:0]
M2 pin function
000
Disable CLK_OUT pin.
001
Disable AUX_OUT pin.
010
Disable CLK_OUT and AUX_OUT.
RModSel[1:0] Modal Parameter Enable.
Force Manual Fractional N Source Selection.
AutoRMod Modal Parameter Override.
FracNSrc Modal Parameter Override
Force AuxOutSrc[1:0] = 10 (PLL Clock Out).
“M2 Mode Pin Functionality” on page 20
011
100
101
110
111
Application:
6.3.7
Clock Input Bandwidth (ClkIn_BW[2:0])
Sets the minimum loop bandwidth when locked to CLK_IN.
ClkIn_BW[2:0]
Minimum Loop Bandwidth
000
1 Hz
001
2 Hz
010
4 Hz
011
8 Hz
100
16 Hz
101
32 Hz
110
64 Hz
111
128 Hz
Application:
“Adjusting the Minimum Loop Bandwidth for CLK_IN” on page 13
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DS758PP1
CIRRUS [ CIRRUS LOGIC ]
