CS2000-CP
8.3.1 R-Mod Selection (RModSel[2:0]) ........................................................................................... 25
8.3.2 Ratio Selection (RSel[1:0]) .................................................................................................... 25
8.3.3 Auxiliary Output Source Selection (AuxOutSrc[1:0]) ............................................................. 26
8.3.4 Enable Device Configuration Registers 1 (EnDevCfg1) ........................................................ 26
8.4 Device Configuration 2 (Address 04h) ........................................................................................... 26
8.4.1 Auto R-Modifier Enable (AutoRMod) ..................................................................................... 26
8.4.2 Lock Clock Ratio (LockClk[1:0]) ............................................................................................ 26
8.4.3 Fractional-N Source for Frequency Synthesizer (FracNSrc) ................................................. 27
8.5 Global Configuration (Address 05h) ............................................................................................... 27
8.5.1 Device Configuration Freeze (Freeze) ................................................................................ 27
8.5.2 Enable Device Configuration Registers 2 (EnDevCfg2) ...................................................... 27
8.6 Ratio 0 - 3 (Address 06h - 15h) ...................................................................................................... 27
8.7 Function Configuration 1 (Address 16h) ........................................................................................ 28
8.7.1 Clock Skip Enable (ClkSkipEn) ............................................................................................. 28
8.7.2 AUX PLL Lock Output Configuration (AuxLockCfg) .............................................................. 28
8.7.3 Reference Clock Input Divider (RefClkDiv[1:0]) .................................................................... 28
8.8 Function Configuration 2 (Address 17h) ........................................................................................ 28
8.8.1 Enable PLL Clock Output on Unlock (ClkOutUnl) ................................................................. 28
8.8.2 Low-Frequency Ratio Configuration (LFRatioCfg) ................................................................ 29
9. CALCULATING THE USER DEFINED RATIO .................................................................................... 30
9.1 High Resolution 12.20 Format ....................................................................................................... 30
9.2 High Multiplication 20.12 Format ................................................................................................... 30
10. PACKAGE DIMENSIONS ................................................................................................................. 31
THERMAL CHARACTERISTICS ......................................................................................................... 31
11. ORDERING INFORMATION .............................................................................................................. 32
12. REFERENCES .................................................................................................................................... 32
13. REVISION HISTORY .......................................................................................................................... 32
LIST OF FIGURES
Figure 1. Typical Connection Diagram ........................................................................................................ 5
Figure 2. Control Port Timing - I²C Format .................................................................................................. 8
Figure 3. Control Port Timing - SPI Format (Write Only) ............................................................................ 9
Figure 4. Delta-Sigma Fractional-N Frequency Synthesizer ..................................................................... 10
Figure 5. Hybrid Analog-Digital PLL .......................................................................................................... 11
Figure 6. Fractional-N Source Selection Overview ................................................................................... 11
Figure 7. Internal Timing Reference Clock Divider ................................................................................... 12
Figure 8. External Component Requirements for Crystal Circuit .............................................................. 12
Figure 9. Ratio Feature Summary ............................................................................................................. 18
Figure 10. PLL Clock Output Options ....................................................................................................... 19
Figure 11. Auxiliary Output Selection ........................................................................................................ 19
Figure 12. Control Port Timing in SPI Mode ............................................................................................. 21
Figure 13. Control Port Timing, I²C Write .................................................................................................. 22
Figure 14. Control Port Timing, I²C Aborted Write + Read ....................................................................... 22
LIST OF TABLES
Table 1. PLL Input Clock Range Indicator ................................................................................................ 13
Table 2. Ratio Modifier .............................................................................................................................. 15
Table 3. Automatic Ratio Modifier ............................................................................................................. 15
Table 4. Example Audio Oversampling Clock Generation from CLK_IN .................................................. 16
Table 5. Example 12.20 R-Values ............................................................................................................ 30
Table 6. Example 20.12 R-Values ............................................................................................................ 30
DS761A2
3
CIRRUS [ CIRRUS LOGIC ]
