CobraNet Hardware User’s Manual
Host Management Interface (HMI)
HADDR[3:0]
HDATA[7:0]
HCS
tiah
LSP
t idhr
MSP
t ias
t idd
t icdr
t idis
HW R
t irpw
t ird
t irdtw
HRD
tirdirqh
HREQ
Figure 16. Parallal Control Port - Intel Mode Read Cycle
HADDR[3:0]
HDATA[7:0]
HCS
t iah
LSP
MSP
t ias
tidhw
ticdw
t idsu
HRD
t iwpw
tiwd
t iwtrd
HW R
tiwrbsyl
HREQ
Figure 17. Parallel Control Port - Intel Mode Write Cycle
DS651UM23
Version 2.3
©Copyright 2005 Cirrus Logic, Inc.
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