CobraNet Hardware User’s Manual
Host Management Interface (HMI)
HREQ may be wired to a host interrupt or DMA request input. HREQ is used to signal the
host that data is available (read case, logic 0) or space is available in the host port data
channel (write case, logic 1).
The read and write case are distinguished by the HMI based on the preceding message.
Identify, Goto Translation (read), Goto Packet (read) and Goto Counters cause HREQ to
represent read status. Goto Translation (write) and Goto Packet (write) switch HREQ to
write mode. All other commands have no effect on HREQ operation.
In general, the host can read from the CS1810xx/CS4961xx when HREQ is low and can
write data to CS1810xx/CS4961xx when HREQ is high.
7.2 Host Port Timing - Motorola® Mode
(C = 20 pF)
L
Parameter
Symbol
Min
5
Max
Unit
ns
Address setup before HEN and HDS low
Address hold time after HEN and HDS low
Read
t
-
-
mas
mah
t
5
ns
Delay between HDS then HEN low or HEN then HDS low
Data valid after HEN and HDS low with HRW high
HEN and HDS low for read
t
0
-
-
19
-
ns
ns
ns
ns
ns
ns
ns
ns
mcdr
t
mdd
t
24
8
mrpw
Data hold time after HEN or HDS high after read
Data high-Z after HEN or HDS high after read
HEN or HDS high to HEN and HDS low for next read
HEN or HDS high to HEN and HDS low for next write
t
-
mdhr
t
-
18
-
mdis
t
30
30
-
mrd
t
-
mrdtw
t
12
HR/W rising to HREQ falling
mrwirqh
Write
Delay between HDS then HEN low or HEN then HDS low
Data setup before HEN or HDS high
HEN and HDS low for write
t
0
8
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
mcdw
t
mdsu
t
24
24
8
mwpw
mrwsu
HRW setup before HEN and HDS low
HRW hold time after HEN or HDS high
Data hold after HEN or HDS high
t
t
mrwhld
t
8
mdhw
HEN or HDS high to HEN and HDS low with HRW high for
next read
t
30
mwtrd
HEN or HDS high to HEN and HDS low for next write
t
30
-
ns
mwd
t
-
12
ns
HRW rising to HREQ falling
mrwbsyl
NOTES:1. The system designer should be aware that the actual maximum speed of the communication port may
be limited by the firmware application. Hardware handshaking on the HREQ pin/bit should be observed
to prevent overflowing the input data buffer.
24
©Copyright 2005 Cirrus Logic, Inc.
DS651UM23
Version 2.3
CIRRUS [ CIRRUS LOGIC ]
