CobraNet Hardware User’s Manual
Host Management Interface (HMI)
7.3 Host Port Timing - Intel® Mode
(C = 20 pF)
L
Parameter
Symbol
Min
Max
Unit
Address setup before HCS and HRD low or HCS and HWR
low
t
5
-
ns
ias
Address hold time after HCS and HRD low or HCS and HWR
high
t
5
-
ns
iah
Read
Delay between HRD then HCS low or HCS then HRD low
Data valid after HCS and HRD low
t
0
-
-
18
-
ns
ns
ns
ns
ns
ns
ns
ns
icdr
t
idd
HCS and HRD low for read
t
24
8
irpw
Data hold time after HCS or HRD high
Data high-Z after HCS or HRD high
t
-
idhr
t
-
18
-
idis
HCS or HRD high to HCS and HRD low for next read
HCS or HRD high to HCS and HWR low for next write
t
30
30
-
ird
t
-
irdtw
t
12
HRD rising to HREQ rising
irdirqhl
Write
Delay between HWR then HCS low or HCS then HWR low
Data setup before HCS or HWR high
HCS and HWR low for write
t
0
8
-
-
ns
ns
ns
ns
ns
ns
ns
icdw
t
idsu
t
24
8
-
iwpw
Data hold after HCS or HWR high
HCS or HWR high to HCS and HRD low for next read
HCS or HWR high to HCS and HWR low for next write
t
-
idhw
iwtrd
t
30
30
-
-
t
-
iwd
t
12
HWR rising to HREQ falling
iwrbsyl
NOTES:1. The system designer should be aware that the actual maximum speed of the communication port may
be limited by the firmware application. Hardware handshaking on the HREQ pin/bit should be observed
to prevent overflowing the input data buffer.
26
©Copyright 2005 Cirrus Logic, Inc.
DS651UM23
Version 2.3
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