CL-PS7500FE
System-on-a-Chip for Internet Appliance
11.13 ID and OD Open-Drain I/O Pins
There are three further open-drain I/O pins:
ID
Intended for use with an ID chip that outputs a unique system ID when the ID
pin is forced low. During power-on reset, the ID output is forced low, and it then
becomes tristate on leaving reset.
OD[1:0]
Could implement a simple serial link.
These are written to through the IOCR and are not capable of generating interrupts. Each pin is forced
low by programming ‘0’ to the appropriate bit in the IOCR. Programming ‘1’ to any bit causes the corre-
sponding pin to tristate, and the value of the input level applied to the pin can then be read back from the
same bit of the IOCR.
NOTE: These three pins do not have pull-up resistors on-chip; be advised that to fit pull-up resistors externally if the
pins are not connected to another device.
11.14 Version and ID Registers
The ID register is composed of two read-only, 8-bit hardwired registers. The lower byte is accessed at
location 0x03200094, and the upper byte at location 0x03200098. Together they should return the value
0xAA7C.
The Version register is accessed at location 0x0320009C, and this is read back the version number of
the device.
NOTE: Under no condition should either of these registers be written; this can cause the chip to enter a test mode.
11.15 Interrupt Control
The CL-PS7500FE interrupt handler takes interrupts from a variety of sources and generates the IRQ or
FIQ interrupt signals required by the ARM processor, depending on the settings of the control and enable
bits in the five sets of interrupt registers. The five sets are:
●
●
●
●
●
FIQ
IRQA
IRQB
IRQC
IRQD
Each of these has a status, mask and request register associated with it, for a total of 15 registers.
Table 11-3 shows the interrupt sources featuring in each set of registers. The polarity entry refers to the
level required at the external pin to set the interrupt. ‘Internal’ means that the interrupt is generated as a
result of an internal state change, as opposed to change on an external pin.
When an interrupt signal is received from one of the interrupt sources, it causes the corresponding bit in
the status register to go high.This bit is then logically AND’ed with the appropriate bit in the mask register,
to create a value in the appropriate bit of the request register. If any of the bits in any of the IRQ request
registers are high, then the CL-PS7500FE generates an internal IRQ interrupt to the ARM processor mac-
rocell, causing the IRQ exception to be taken. If any of the bits in the FIQ request register are high, the
CL-PS7500FE generates an internal FIQ interrupt to the ARM processor, causing the FIQ exception to
be taken.
June 1997
121
ADVANCE DATA BOOK v2.0
I/O SUBSYSTEMS
CIRRUS [ CIRRUS LOGIC ]
