CL-PS7500FE
System-on-a-Chip for Internet Appliance
is not exceeded under the worst case conditions. The A-to-D converter is effectively providing a digital
count directly related to the value of the resistance in the RC circuit.
11.11 Timers
The CL-PS7500FE includes two general-purpose timers used as interrupt sources. Each timer is imple-
mented as a 16-bit down counter, and has an input latch and an output latch associated with it. The
counter decrements continuously, clocked at 2 MHz. When it reaches zero, it is reloaded from the input
latch and the down count restarts.
There are four 8-bit-wide registers associated with the two timers. Each timer has:
●
two eight bit registers corresponding to the 16-bits of the timer
●
two further write-only registers that cause the GO and LATCH commands to be issued to the appropriate
timer when written to
Figure 11-1 shows the timer configuration.
LATCH LOW
LATCH HIGH
CONTROL
LOGIC
2 MHZ
GO
16-BIT COUNTER
COUNT HIGH
COUNT LOW
LATCH
DATA[7:0]
Figure 11-1. Timer Configuration
June 1997
119
ADVANCE DATA BOOK v2.0
I/O SUBSYSTEMS
CIRRUS [ CIRRUS LOGIC ]
