CL-PS7500FE
System-on-a-Chip for Internet Appliance
received from the peripheral, the KDATA/MSDATA line is pulled low as a start bit. Each data bit is set up
to the falling edge of the clock. Eight data bits are transmitted from the keyboard/mouse, followed by a
parity bit (odd parity) and a high stop bit.
When CL-PS7500FE transmits a byte to the peripheral, the KCLK/MSCLK line is pulled low, then allowed
to float and the KDATA/MSDATA line is pulled low, as a request to send.The keyboard/mouse then drives
the clock, causing CL-PS7500FE to put eight bits of serial data out onto the KDATA/MSDATA line. A parity
bit is driven out, followed by a stop bit, and the stop bit may be acknowledged by the peripheral
(the CL-PS7500FE does not check on the acknowledge).
11.10 Analog-to-Digital Converter Interface
CL-PS7500FE contains four analog comparators with 16-bit timers, designed primarily for the implemen-
tation of an analog joystick interface. Each converter is of the slope integration type, using an external RC
network attached to the appropriate ATOD[3:0] pin to generate a variable ramp delay.
The time taken for the voltage at the input to the comparator to reach the comparator’s threshold is mea-
sured by a 16-bit counter that stopped when the threshold of the comparator is reached. At this point an
internal ‘stop’ flag for that channel is set. The value is held in the counter until it has been read and the
channel is then reset.
Discharge transistors on the analog inputs are used to discharge the external capacitor and to initiate a
new integration cycle.
11.10.1 Counters
Each of the four counters can be reset by programming one of four bits in the ATODCR register. The four
counters cannot be written to but can be read at addresses as follows:
CNT1 (0x032000EC)
CNT2 (0x032000F0)
CNT3 (0x032000F4)
CNT4 (0x032000F8)
counter 1
counter 2
counter 3
counter 4
The four counters are implemented as simple asynchronous ripple counters, and it is therefore important
that they should not be read until the ‘stop’ flag for that particular channel is set, as indicated in the status
register, to indicate that the counter stopped and the read back value is stable.
11.10.2 Interrupt Control
There is a single bit in the main CL-PS7500FE interrupt handling registers (bit 2 of the IRQD set) that can
accept an interrupt from the A-to-D converters.Thus, some interrupt pre-processing is done to determine
how this main interrupt is to be generated. An interrupt control register is provided so that various combi-
nations of channels can generate the final interrupt.
There are four possible interrupt sources, one for each channel, and each channel attempts to generate
an interrupt when the comparator threshold is reached and the ‘stop’ flag is set internally.
Each of these interrupt sources can be individually enabled using the lower four bits of the Interrupt Con-
trol register, and the upper four bits determine the combination of bits that create the main interrupt
passed to the IRQD registers.
116
June 1997
I/O SUBSYSTEMS
ADVANCE DATA BOOK v2.0
CIRRUS [ CIRRUS LOGIC ]
