CL-PD6833
PCI-to-CardBus Host Adapter
8.3
Power Control — PME _CXT
Register Name: Power Control — PME_CXT
I/O Index: 02h
Register Per: socket
Register Compatibility Type: 365
Memory Offset: 802h
Bit 7
Card Enable Compatibility
R/W:0 R/W:0
Bit 6
Bit 5
Bit 4
Power
Bit 3
Compatibility
R/W:00
Bit 2
Bit 1
Bit 0
1 Power
Reserved
R/W:0
V
V
CC
R/W:0
PP
R/W:00
NOTE: PME_CXT (PME Context) is a set of register bits that do not get reset or initialized if PME Enable is true
when the CL-PD6833 changes power states from D3 to D0 through a software PCI Bus Segment reset.
This register is write-protected by writes to the Event Force register. The register is not write protected
when a CV test completes. CV test can be started by a card insertion or by a write to bit 14 of the Event
Force register. Use either the Control register (see page 82) or this Power Control register to set card
power. Do not use both registers.
Table 8-2. Enabling of Socket Power Commands
Interface Status
Register
(see page 92)
Power Control
Register
VCC
Both CD1#
RST# Level and CD2# Are
Active (Low)
VPP
Command to
Power Device
Command
to Power
Device
VCC Power (Bit 4)
Card Power On (Bit 6)
Low
High
High
X
X
X
0
0
0
Inactive (high)
Inactive (high)
Inactive (high)
Inactive (low)
Inactive (low)
Inactive (low)
No
X
X
Activated by bit Activated by
1 of the Misc bits 1 and 0 of
High
Yes
1
1
Control 1
the
Power
register
Control register
Table 8-3. Enabling of PC Card Output Signals to Socket
Both CD1# and
CD2# Are
Active (Low)
Power Control Register
VCC Power (Bit 4)
Card Enable (Bit 7a)
State of the CL-PD6833 VCC
Command to Power Device
RST# Level
Low
High
High
High
High
High
X
X
X
0
0
1
1
X
X
0
1
0
1
High-impedance
High-impedance
High-impedance
Enabled
No
Yes
Yes
Yes
Yes
High-impedance
Enabled
a
This only applies to PC Card 16 (R2) cards.
94
June 1998
DEVICE CONTROL REGISTERS
ADVANCE DATA BOOK v0.3
CIRRUS [ CIRRUS LOGIC ]
