CL-PD6833
PCI-to-CardBus Host Adapter
8.
DEVICE CONTROL REGISTERS
Table 8-1. Device Control Registers Quick Reference
Register Name
Chip Revision
I/O Index
Memory Offset
Page Number
00h
01h
02h
800h
801h
802h
91
92
94
Interface Status
Power Control — PME _CXT
Interrupt and General Control —
PME_CXT
03h
04h
05h
06h
803h
804h
805h
–
96
98
Card Status Change — PME_CXT
Management Interrupt Configuration
— PME_CXT
99
Mapping Enable
101
8.1
Chip Revision
Register Name: Chip Revision
I/O Index: 00h
Register Per: chip
Register Compatibility Type: 365
Memory Offset: 800h
Bit 7
Bit 6
Bit 5
Reserved
R:0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Interface ID
R:10
Reserved
R:0
Revision
a
R:0010
a
Value for the current stepping only.
Bits 3:0 — Revision
This field indicates the compatibility of the CL-PD6833 with the Intel 82365SL A-step.
Bits 5:4 — Reserved
These bits always read ‘0’s.
Bits 7:6 — Interface ID
Bit 7
Bit 6
Interface Supported
0
0
1
1
0
1
0
1
I/O only
Memory only
Memory and I/O
Reserved
These bits identify the type of interface this controller supports. The CL-PD6833 supports both
memory and I/O interface PC Cards.
June 1998
91
ADVANCE DATA BOOK v0.3
DEVICE CONTROL REGISTERS
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