CL-PD6833
PCI-to-CardBus Host Adapter
8.5
Card Status Change — PME_CXT
Register Name: Card Status Change — PME_CXT
I/O Index: 04h
Register Per: socket
Register Compatibility Type: 365
Memory Offset: 804h
Bit 7
Bit 6
Bit 5
R:0
Bit 4
R:0
Bit 3
Bit 2
Bit 1
Bit 0
Battery
Warning
Change
Battery Dead
Or Status
Change
Card Detect
Change
Ready
Change
Reserved
R:0
R:0
R:0
R:0
R:0
R:0
NOTE: PME_CXT (PME Context) is a set of register bits that do not get reset or initialized if PME Enable is true
when the CL-PD6833 changes power states from D3 to D0 through a software PCI Bus Segment reset.
This register indicates the source of a management interrupt generated by the CL-PD6833.
Bit 0 — Battery Dead Or Status Change
0
A transition (from high to low in Memory Card Interface mode or either high to low or low to high in I/O
Card Interface mode) on the BVD1/STSCHG#/RI# pin has not occurred since this register was last
read.
1
A transition on the BVD1/STSCHG#/RI# pin has occurred.
In Memory Card Interface mode, this bit is set to ‘1’ when the BVD1/STSCHG#/RI# pin (see
page 20) changes from high to low, indicating a battery dead condition. In I/O Card Interface
mode, this bit is set to ‘1’ when the BVD1/STSCHG#/RI# pin changes from either high to low or
low to high. In I/O Card Interface mode, the function of this bit is not affected by bit 7 of the
Interrupt and General Control register. This bit is reset to ‘0’ whenever this register is read.
Bit 1 — Battery Warning Change
0
A transition (from high to low) on the BVD2/SPKR#/LED# pin has not occurred since this register was
last read.
1
A transition on the BVD2/SPKR#/LED# pin has occurred.
In Memory Card Interface mode, this bit is set to ‘1’ when the BVD2/SPKR#/LED# pin changes
from high to low, indicating a battery warning. This bit is not valid in I/O Card Interface mode. This
bit is reset to ‘0’ whenever this register is read.
Bit 2 — Ready Change
0
A transition on the RDY/IREQ# pin has not occurred since this register was last read.
A transition on the RDY/IREQ# pin has occurred.
1
This bit is ‘1’ when a change has occurred on the RDY/IREQ# pin (see page 18). This bit is reset
to ‘0’ whenever this register is read. This bit is not valid in I/O Card Interface mode.
Bit 3 — Card Detect Change
0
1
A transition on neither the CD1# nor the CD2# pin has occurred since this register was last read.
A transition on either the CD1# or the CD2# pin or both has occurred.
This bit is set to ‘1’ when a change has occurred on the CD1# or CD2# pin (see page 18). This bit
is reset to ‘0’ whenever this register is read.
Bits 7:4 — Reserved
These bits read ‘0’s.
98
June 1998
DEVICE CONTROL REGISTERS
ADVANCE DATA BOOK v0.3
CIRRUS [ CIRRUS LOGIC ]
