CL-PD6710/’22
ISA–to–PC-Card Host Adapters
Bit 5 — Pull-up Control
0
1
Pull-ups on CD2, CD1, A_GPSTB, and B_GPSTB (CL-PD6722) are in use.
Pull-ups on CD2, CD1, A_GPSTB, and B_GPSTB (CL-PD6722) are turned off.
This bit turns off the pull-ups on CD2, CD1, and A_GPSTB and B_GPSTB (CL-PD6722). Turning
off these pull-ups can be used in addition to Suspend mode to even further reduce power when
cards are inserted but no card accessibility is required. Even though power may or may not still be
applied, all pull-ups and their associated inputs will be disabled.
Bit 7:6 — DMA Enable (CL-PD6722 only)
On the CL-PD6722, DMA Enable bits 6 and 7 enable the DMA operation of the PC Card socket.
At reset these bits are set to ‘0’, and this is non-DMA mode. If either or both of these bits is set,
the socket is in DMA mode. The three codes that cause DMA mode also select the use of one of
three pins for the active-low -DREQ input at the PC Card interface.
Bit 7
Bit 6
Pin Used
-INPACK
0
1
1
1
0
1
WP/-IOIS16
BVD2/-SPKR
For cards requiring DMA services but also needing input acknowledge functionality, or needing to
indicate the size of I/O registers within a window, or needing digital speaker or LED operation, the
selection of the -DREQ signal to the socket is made to be as flexible as possible.
9.7.3
Maximum DMA Acknowledge Delay (CL-PD6722 only)
Register Name: Maximum DMA
Register Per: socket
Acknowledge Delay
Register Compatibility Type: ext.
Extended Index: 04h
Bit 4 Bit 3
Index: 2Fh
Bit 7
Bit 6
Bit 5
Bit 2
Bit 1
Bit 0
Maximum DMA Acknowledge Delay
RW:00000000
During a DMA data transfer process, an ISA-based system typically follows its issuance of a DMA
acknowledge with a DMA read or write cycle. However, during a DMA write-verify operation, a system can
issue a DMA acknowledge without following it with a DMA read or write cycle. Because a DMA-capable
PC Card receives DMA acknowledgment only by reception of a DMA read or write cycle, conditions may
occur where the card never receives a DMA acknowledge. To prevent this from happening in an ISA-
based system, a maximum DMA acknowledge delay feature has been added that generates a ‘dummy’
DMA write cycle (reads DMA data from the card) if there are no system-generated DMA read or write
cycles to the card within a programmable time.
Once a DMA acknowledge is received from the system, the CL-PD6722 starts counting the time from the
assertion of the DACK* signal until the system issues a DMA read or write command (IOR* or IOW*). If
this interval exceeds the programmed time, the CL-PD6722 assumes that a system write-verify is in
progress and generates a dummy DMA write cycle at the PC Card interface. This allows the passing of
the DMA acknowledge (and terminal count status) to the card so it can perform any intended verify-cycle
functions.
May 1997
67
PRELIMINARY DATA SHEET v3.1
EXTENSION REGISTERS
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