CL-GD62XX
LCD VGA Controller Family
1.2 Pin Diagram for the CL-GD6215
CRT VDD
Group
Memory VDD Group (DVDD)
Panel VDD Group (PVDD) (AVDD3)
Bus VDD Group (BVDD)
MD3
121
80
79
TWR*
DVDD2
122
RED
CRT V
DD
MD2
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
123
GREEN
BLUE
AVSS2
HSYNC
VSYNC
AVDD2
DUALCAS
NPD
[R5]
[R4]
INTCLK*
LCDRSET*
SW3
SW2
SW1
[R3]
[R2]
[G5]
[G4]
[G3]
VSS4
[B5]
[B4]
CVDD1
[B3]
AVDD1
VFILTER
AVSS1
SD7
Group
(AVDD2)
MD1
124
125
126
127
128
129
130
131
132
133
MD0
WE0*
CAS*
RAS*
MA9
OE*
MA8
MA7
MA6
Bus V
DD
Group
(BVDD)
(PVDD)
MA5
MA4
MA3
MA2
MA1
VSS9
Bus V
DD
Group
(BVDD)
134
135
136
137
138
139
CL-GD6215
160-Pin PQFP
MA0
AVDD4
MFILTER
AVSS4
32KHz
OSC
CLK1X
CVDD2
SD15
SD14
SD13
SD12
VSS10
SD11
SD10
SD9
140
141
142
143
144
145
146
147
148
149
150
MCLK
VCO
V
DD
(PVDD)
VCLK
(AVDD4)
VCO V
DD
(AVDD1)
50
49
151
152
SD6
SD5
VSS3
SD4
SD3
SD2
SD1
SD0
48
47
46
45
44
43
42
41
153
154
155
156
157
158
159
160
SD8
LA17
LA18
EROM*
VSS11
BVDD2
Bus V Group (BVDD)
DD
NOTES:
1) All pins in ‘[ ]’ are color TFT data interface pins.
2) All pins in ‘{ }’ are PI bus interface pins.
3) Power pin signal names are in bold type.
12
October 1993
PIN INFORMATION
PRELIMINARY DATA BOOK
CIRRUS [ CIRRUS LOGIC ]
