CL-GD62XX
LCD VGA Controller Family
List of Figures
Figure 2–1. Typical Memory Clock Filter . . . . . . . .35
Figure 2–2. Typical Video Clock Filter . . . . . . . . . .35
Figure 7–1. Bus Signal Timing (ISA Bus). . . . . . .131
Figure 7–2. BALE Timing (ISA Bus). . . . . . . . . . .132
Figure 7–3. EROM* Timing (ISA Bus) . . . . . . . . .133
Figure 7–4. AEN Timing (ISA Bus). . . . . . . . . . . .133
Figure 7–5. PI Bus Interface Timing. . . . . . . . . . .135
Figure 7–10. BRDY# Delay (Local Bus). . . . . . . . .140
Figure 7–11. Read Data Timing (Local Bus) . . . . .140
Figure 7–12. Buffer Control Timing: 16-Bit Cycle
(’486 Local Bus) . . . . . . . . . . . . . . . .141
Figure 7–13. Display-Memory Bus Read Timing
(t = MCLK) . . . . . . . . . . . . . . . . . . . .143
Figure 7–14. Display-Memory Bus Write Timing . .145
Figure 7–15. CAS*-Before-RAS* Refresh Timing
(Display Memory Bus). . . . . . . . . . . .146
Figure 7–6. CLK1X, CLK2X Timing
(Local Bus) . . . . . . . . . . . . . . . . . . . .136
Figure 7–16. Reset Timing. . . . . . . . . . . . . . . . . . .147
Figure 7–7. Reset Timing (Local Bus) . . . . . . . . .137
Figure 7–17. STN Monochrome and Color-Passive
LCD Interface Timing . . . . . . . . . . . .149
Figure 7–8. ADS#, LBA# Timing (Local Bus)
(Not Pipelined) . . . . . . . . . . . . . . . . .138
Figure 7–18. TFT, EL , Plasma Color, and
Monochrome Single-Scan LCD Interface
Timing . . . . . . . . . . . . . . . . . . . . . . . .151
Figure 7–9. LBA#, BS16# Timing (Local Bus)
(Pipelined). . . . . . . . . . . . . . . . . . . . .139
List of Tables
Table 1–1.
Table 1–2.
Table 1–3.
Table 1–4.
Table 1–5.
Table 1–6.
Table 1–7.
Table 1–8.
Table 4–1.
Host Interface . . . . . . . . . . . . . . . . . . .19
Table 7–4.
Table 7–5.
Table 7–6.
AEN Timing (ISA Bus). . . . . . . . . . . .133
PI Bus-Interface Timing. . . . . . . . . . .134
CRT Interface . . . . . . . . . . . . . . . . . . .20
LCD Flat Panel Interface. . . . . . . . . . .20
Display Memory Interface . . . . . . . . . .21
Power Management Pins . . . . . . . . . .22
Synchronizer/Clock Interface . . . . . . .22
Miscellaneous Pins . . . . . . . . . . . . . . .22
Power and Ground . . . . . . . . . . . . . . .23
CLK1X, CLK2X Timing
(Local Bus) . . . . . . . . . . . . . . . . . . . .136
Table 7–7.
Table 7–8.
Reset Timing (Local Bus) . . . . . . . . .137
ADS#, LBA# Timing (Local Bus)
(Not Pipelined) . . . . . . . . . . . . . . . . .138
Table 7–9.
LBA#, BS16# Timing (Local Bus)
(Pipelined). . . . . . . . . . . . . . . . . . . . .139
IBM Standard VGA Video
Modes . . . . . . . . . . . . . . . . . . . . . . . . .59
Table 7–10. BRDY# Delay (Local Bus). . . . . . . . .140
Table 7–11. Read Data Timing (Local Bus) . . . . .140
Table 4–2.
Cirrus Logic Extended CRT Video
Modesa . . . . . . . . . . . . . . . . . . . . . . . .60
Table 7–12. Buffer Control Timing: 16-Bit Cycle
(’486 Local Bus) . . . . . . . . . . . . . . . .141
Table 4–3.
Table 4–4.
IBM Standard VGA Video Modes . . . .61
Table 7–13. Display-Memory Bus Read Timing
(tb = MCLK) . . . . . . . . . . . . . . . . . . .142
Cirrus Logic Extended LCD Video
Modea. . . . . . . . . . . . . . . . . . . . . . . . .61
Table 7–14. Display-Memory Bus Write Timing
(tb = MCLK) . . . . . . . . . . . . . . . . . . .144
Table 5–1.
Table 6–1.
VGA Register Port Map. . . . . . . . . . . .63
512K-Byte Memory with 4K-Byte
Granularity and VGA Mapping . . . . . .89
Table 7–15. CAS*-Before-RAS* Refresh Timing
(Display Memory Bus). . . . . . . . . . . .146
Table 6–2.
Table 6–3.
Typical Power-Down Timer
Settings. . . . . . . . . . . . . . . . . . . . . . .105
Table 7–16. Reset Timing. . . . . . . . . . . . . . . . . . .147
Table 7–17. STN Monochrome and Color-Passive
LCD Interface Timing . . . . . . . . . . . .148
Programming the Graphics Hardware
Cursor . . . . . . . . . . . . . . . . . . . . . . . .124
Table 7–18. TFT Color Single-Scan LCD Interface
Timing, . . . . . . . . . . . . . . . . . . . . . . .150
Table 7–0.
Table 7–1.
Table 7–2.
Table 7–3.
Output Loading Values Table . . . . . .127
Bus Signal Timing (ISA Bus). . . . . . .130
BALE Timing (ISA Bus). . . . . . . . . . .132
EROM* Timing (ISA Bus) . . . . . . . . .133
Table 7–19. Frequency Synthesizer Input Clock
Specification . . . . . . . . . . . . . . . . . . .152
October 1993
5
PRELIMINARY DATA BOOK
CIRRUS [ CIRRUS LOGIC ]
