CL-GD62XX
LCD VGA Controller Family
Table of Contents (cont.)
6.1.31 CR23: Suspend Mode Input Switch Debounce
Timer.............................................................102
6.1.32 CR25: CL-GD62XX Part Status
Register.........................................................103
6.1.33 CR27: CL-GD62XX Part ID Register ...........104
5. VGA REGISTER PORT MAP.............. 59
6. REGISTER INFORMATION................. 61
6.1 CL-GD62XX Extended-Register Details ............65
6.1.1 SR6: Unlock All CL-GD62XX Register
Extensions.......................................................65
6.1.2 SR7: Extended Sequencer Modes .................66
6.1.3 SR8: Miscellaneous Control............................67
6.1.4 SR9, SRA, SR14, SR15, SR19: Scratch-Pad
Registers 0-4...................................................69
6.1.5 SRB, SRC, SRD, SRE: VCLK0, 1, 2, 3
Numerator Value .............................................70
6.1.34 CR29: CL-GD62XX Configuration
Register.........................................................105
6.1.35 R0X: LCDTiming Register — HorizontalTotal for
80-Column and Mode 13h............................106
6.1.36 R1X: LCD Timing Register — Horizontal Total
Enable and 40-Column Horizontal Total.......107
6.1.37 R2X: LCD Timing — LFS Vertical Counter Value
Compare (3C2[7:6] = ‘11’) ............................108
6.1.6 SRF: DRAM Control........................................71
6.1.7 SR10, 30, 50, 70, 90, B0, D0, F0: Graphics
Cursor X Position ............................................73
6.1.38 R3X: LCD Timing — LFS Vertical Counter Value
Compare (3C2[7:6] = ‘10’)............................109
6.1.8 SR11, 31, 51, 71, 91, B1, D1, F1: Graphics
Cursor Y Position ............................................74
6.1.39 R4X: LCD Timing — LFS Vertical Counter Value
Compare (3C2[7:6] = ‘01’)............................ 110
6.1.9 SR12: Graphics Cursor Attributes...................75
6.1.10 SR13: Graphics Cursor Pattern
6.1.40 R5X: LCD Timing — LFS Vertical Counter Value
Compare (3C2[7:6] = ‘00’).............................111
Address Offset.................................................76
6.1.11 SR16: Miscellaneous Control 2 ......................77
6.1.41 R6X: LCD Timing — Overflow (Most-Significant)
Bits for LFS Signal Compare........................ 112
6.1.12 SR1A: Dual-Scan Color Control
6.1.42 R7X: LCD Timing — Panel Signal Control for
Color TFT Panels.......................................... 113
(CL-GD6235 only)...........................................78
6.1.13 SR1B, SR1C, SR1D, SR1E: VCLK0, 1, 2, 3
Denominator and Post Scalar Value...............79
6.1.43 R8X: LCD Timing — STN Color Panel Data
Format........................................................... 114
6.1.14 SR1F: Memory Clock Frequency
6.1.44 R9X: LCD Timing — TFT Panel
Programming...................................................80
Data Format.................................................. 115
6.1.15 STAT: Input Status Register 1.........................81
6.1.16 GR0: Set/Reset Register (CL-GD62XX
Extensions)......................................................82
6.1.45 RAX: LCDTiming —TFTPanel HSYNC Position
Control .......................................................... 116
6.1.46 RBX: LCD Timing — Special Functions for
CL-GD6235 Only.......................................... 117
6.2 132-Column Alphanumeric Mode .................... 118
6.1.17 GR1: Enable Set/Reset Register
(CL-GD62XX Extensions)...............................83
6.2.1 Write Buffer and Display FIFO...................... 118
6.3 Hardware Cursor.............................................. 118
6.4 Graphics Hardware Cursor..............................120
6.1.18 GR5: Mode Register
(CL-GD62XX Extensions)...............................84
6.1.19 GR9: Offset Register 0....................................85
6.1.20 GRA: Offset Register 1 ...................................86
7. ELECTRICAL SPECIFICATIONS..... 121
6.1.21 GRB: Graphics Controller
7.1 Absolute Maximum Ratings.............................121
7.2 DC Specifications (Digital) ..............................122
7.3 DC Specifications (Palette DAC) .....................123
7.4 DC Specifications
Mode Extensions.............................................87
6.1.22 CR19: Interlace End........................................88
6.1.23 CR1A: Interlace Control..................................89
6.1.24 CR1B: Extended Display Controls..................90
6.1.25 CR1C: Flat-Panel Interface.............................92
6.1.26 CR1D: Flat-Panel Display Controls ................94
6.1.27 CR1E: Flat-Panel Shading..............................96
6.1.28 CR1F: Flat Panel Modulation Control.............98
6.1.29 CR20: Power Management Register..............99
6.1.30 CR21: Power-Down Timer Control ...............101
(Frequency Synthesizer)..................................124
7.5 DAC Characteristics.........................................124
7.6 List of Waveforms ............................................125
8. PACKAGE DIMENSIONS ................. 149
9. ORDERING INFORMATION ............. 150
9.1 Package Marking Numbering Guide................150
4
October 1993
TABLE OF CONTENTS
PRELIMINARY DATA BOOK
CIRRUS [ CIRRUS LOGIC ]
