CS4365
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI™ FORMAT
(Inputs: Logic 0 = GND, Logic 1 = VLC, C = 30 pF)
L
Parameter
CCLK Clock Frequency
Symbol
Min
-
Max
Unit
MHz
ns
f
6
-
sclk
RST Rising Edge to CS Falling
t
500
500
srs
CCLK Edge to CS Falling
(Note 17)
t
-
ns
spi
CS High Time Between Transmissions
CS Falling to CCLK Edge
CCLK Low Time
t
1.0
20
66
66
40
15
-
-
-
-
-
-
µs
ns
ns
ns
ns
ns
csh
t
css
t
scl
CCLK High Time
t
sch
dsu
CDIN to CCLK Rising Setup Time
t
CCLK Rising to DATA Hold Time
(Note 18)
t
dh
Rise Time of CCLK and CDIN
(Note 19)
t
-
-
100
100
ns
ns
r2
Fall Time of CCLK and CDIN
(Note 19)
t
f2
Notes:
17.
18. Data must be held for sufficient time to bridge the transition time of CCLK.
19. For F < 1 MHz.
t
only needed before first falling edge of CS after RST rising edge. t = 0 at all other times.
spi spi
SCK
RST
t
t
srs
CS
t
t
t
spi css
scl
sch
t
csh
CCLK
t
t
r2
f2
CDIN
t
t
dsu
dh
Figure 6. Control Port Timing - SPI Format
DS670PP1
17
CIRRUS [ CIRRUS LOGIC ]
