CS42L51
4. APPLICATIONS
4.1
Overview
4.1.1
Architecture
The CS42L51 is a highly integrated, low power, 24-bit audio CODEC comprised of stereo analog-to-digital
converters (ADC), and stereo digital-to-analog converters (DAC) designed using multi-bit delta-sigma
techniques. The DAC operates at an oversampling ratio of 128Fs and the ADC operates at 64Fs, where
Fs is equal to the system sample rate. The different clock rates maximize power savings while maintaining
high performance. The CODEC operates in one of four sample rate speed modes: Quarter, Half, Single
and Double. It accepts and is capable of generating serial port clocks (SCLK, LRCK) derived from an input
Master Clock (MCLK).
4.1.2
Line & MIC Inputs
The analog input portion of the CODEC allows selection from and configuration of multiple combinations
of stereo and microphone (MIC) sources. Six line inputs with configuration for two MIC inputs (or one MIC
input with common mode rejection), two MIC bias outputs and independent channel control (including a
high-pass filter disable function) are available. A Programmable Gain Amplifier (PGA), MIC boost, and Au-
tomatic Level Control (ALC), with noise gate settings, provide analog gain and adjustment. Digital volume
controls, including gain, boost, attenuation and inversion are also available.
4.1.3
4.1.4
Line & Headphone Outputs
The analog output portion of the CODEC includes a headphone amplifier capable of driving headphone
and line-level loads. An on-chip charge pump creates a negative headphone supply allowing a full-scale
output swing centered around ground. This eliminates the need for large DC-Blocking capacitors and al-
lows the amplifier to deliver more power to headphone loads at lower supply voltages. Eight gain settings
for the headphone amplifier are available.
Signal Processing Engine
A signal processing engine is available to process serial input data (PCM) and ADC data before output to
the DAC. The ADC and PCM data have independent volume controls and mixing functions such as mono
mixes and left/right channel swaps. A Tone Control provides bass and treble at four selectable corner fre-
quencies. An automatic level control provides limiting capabilities at programmable attack and release
rates, maximum thresholds and soft ramping. A 15/50 µs de-emphasis filter is also available at a 44.1 kHz
sample rate.
4.1.5
4.1.6
Beep Generator
A beep may be generated internally at select frequencies across approximately two octave major scales
and configured to occur continuously, periodically or at single time intervals controlled by the user. Volume
may be controlled independently.
Device Control (Hardware or Software Mode)
In software mode, all functions and features may be controlled via a two-wire I²C or three-wire SPI control
port interface. In hardware mode, a limited feature set may be controlled via stand-alone control pins.
4.1.7
Power Management
Two software mode control registers provide independent power down control of the ADC, DAC, PGA,
MIC pre-amp and MIC bias, allowing operation in select applications with minimal power consumption.
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DS679A2
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