CS42L51
SWITCHING CHARACTERISTICS - SPI CONTROL PORT
(Inputs: Logic 0 = DGND, Logic 1 = VL)
Parameter
Symbol
fsck
tsrs
Min
0
Max
Units
MHz
ns
CCLK Clock Frequency
6.0
20
20
1.0
66
66
40
15
-
-
RESET Rising Edge to CS Falling
CS Falling to CCLK Edge
tcss
tcsh
tscl
-
ns
CS High Time Between Transmissions
CCLK Low Time
-
µs
-
ns
CCLK High Time
tsch
tdsu
tdh
-
-
ns
CDIN to CCLK Rising Setup Time
CCLK Rising to DATA Hold Time
Rise Time of CCLK and CDIN
Fall Time of CCLK and CDIN
ns
(Note 19)
(Note 20)
(Note 20)
-
ns
tr2
100
100
ns
tf2
-
ns
Notes:
19. Data must be held for sufficient time to bridge the transition time of CCLK.
20. For f <1 MHz.
sck
RST
tsrs
CS
tcsh
tcss
tsch
tscl
tr2
CCLK
tf2
tdsu
tdh
CDIN
Figure 8. Control Port Timing - SPI Format
DS679A2
23
CIRRUS [ CIRRUS LOGIC ]
