CS42L51
SWITCHING SPECIFICATIONS - I²C CONTROL PORT
(Inputs: Logic 0 = DGND, Logic 1 = VL, SDA C = 30 pF)
L
Parameter
SCL Clock Frequency
Symbol
fscl
Min
-
Max
Unit
kHz
ns
100
tirs
500
4.7
4.0
4.7
4.0
4.7
0
-
RESET Rising Edge to Start
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low time
tbuf
-
µs
thdst
tlow
-
µs
-
µs
Clock High Time
thigh
tsust
thdd
tsud
trc
-
µs
Setup Time for Repeated Start Condition
-
µs
SDA Hold Time from SCL Falling
SDA Setup time to SCL Rising
Rise Time of SCL and SDA
(Note 18)
-
µs
250
-
-
1
ns
µs
Fall Time SCL and SDA
tfc
-
300
-
ns
Setup Time for Stop Condition
Acknowledge Delay from SCL Falling
tsusp
tack
4.7
300
µs
1000
ns
Notes:
18. Data must be held for sufficient time to bridge the transition time, t , of SCL.
fc
RST
t
irs
Repeated
Start
Stop
Start
Stop
SDA
SCL
t
t
t
t
t
buf
t
high
hdst
f
susp
hdst
t
t
t
t
t
r
sust
sud
low
hdd
Figure 7. Control Port Timing - I²C
22
DS679A2
CIRRUS [ CIRRUS LOGIC ]
