CDB42406
1.7.1b
Setup 1
Using the recovered clock from the S/PDIF input data stream, the CS8416 masters MCLK,
subclocks and data for the DAC. A DSP connected to the DSP I/O HDR masters the sub-
clocks for the ADC and CS8406. For implementation of this setup option, set DIP switch
S4 (SW[3:0]) to ‘0001’b.
CS8416
R MC K
MC LK
DAC _LR C K/
DAC _SCL K
DAC _SDINx
ADC _L RC K/
ADC _SC LK
AD C_ SDO UT
CS42406
AUD IO
M CLK
O MC K
OL RC K/
O SC LK
SD OU T
CS8406
OM CK
IL RC K/
ISC LK
SD IN
DSP I/O
H DR
D SP_MC LK
DSP_D AC _L RC K/
DSP_D AC_SC LK
DSP_SD IN x
DSP_ADC _L RC K/
DSP_AD C_SC LK
DSP_SD OU T
Figure 2. S/PDIF IN/OUT - Setup 1
1.7.1c
Setup 2
Using the recovered clock from the S/PDIF input data stream, the CS8416 masters MCLK,
subclocks and data for the DAC. The ADC masters its own subclocks. For implementation
of this setup option, set DIP switch S4 (SW[3:0]) to ‘0010’b.
CS8416
RMC K
MC LK
DAC _LR CK/
DAC _SCLK
DAC _SDIN x
ADC _LR C K/
ADC _SCL K
ADC _SDO UT
C S42406
AUDIO
MCLK
O MC K
O LRC K/
O SC LK
SD OU T
CS8406
OMC K
I LRC K/
I SC LK
SD IN
DSP I/O
HDR
DSP_MC LK
D SP_ DAC_ LRC K/
D SP_ DAC_ SC LK
D SP_SD INx
D SP_ AD C_ LRC K/
D SP_ AD C_ SC LK
D SP_SD OU T
Figure 3. S/PDIF IN/OUT - Setup 2
7
CIRRUS [ CIRRUS LOGIC ]
