CDB42406
1.4
Canned Oscillator
Oscillator Y1 provides a System Clock. This clock can be routed through the CS8416 out the
RMCK pin when the S/PDIF input is disconnected (refer to the CS8416 data sheet for details
on OMCK operation). To use the canned oscillator as the source of the MCLK signal, select
from one of the pre-defined options, detailed in section 1.7, using the SW[3:0] positions on
switch S4.
The oscillator is mounted in pin sockets, allowing easy removal or replacement. The board is
shipped with a 12.2880 MHz crystal oscillator stuffed at Y1.
1.5
Analog Input
RCA connectors supply the CS42406 analog inputs through unity gain, AC-coupled single-
ended circuits. A 1 Vrms single-ended signal will drive the CS42406 inputs to full scale.
1.6
Analog Outputs
The CS42406 analog outputs are routed through a single-pole RC filter. The corner frequen-
cy can be extended to 190 kHz by simply removing one of the 1500 pF filter capacitors.
1.7
CPLD Board Setup
The CPLD (U9) controls all digital signal routing between the CS42406, CS8416, CS8406,
AUDIO MCLK (Y1), and DSP I/O HDR. The user may choose from 14 clock/data routing op-
tions by setting certain combinations of switch S4. See sections 1.7.1 through 1.7.4 for a de-
scription of each mode. Any combination can be realized in either stand-alone or control port
mode.
5
CIRRUS [ CIRRUS LOGIC ]
