CS5166
Application Information: continued
back pin (V
FB
) to the output capacitors and load and car-
ries the output current. With no load, there is no DC drop
across this resistor, producing an output voltage tracking
the Error amps, including the +25mV offset. When the full
load current is delivered, a 50mV drop is developed across
this resistor. This results in output voltage being offset -
25mV low.
The result of Adaptive Voltage Positioning is that addition-
al margin is provided for a load transient before reaching
the output voltage specification limits. When load current
suddenly increases from its minimum level, the output
capacitor is pre-positioned +25mV. Conversely, when load
current suddenly decreases from its maximum level, the
output capacitor is pre-positioned -25mV (see Figures 8, 9,
and 10). For best Transient Response, a combination of a
number of high frequency and bulk output capacitors are
usually used.
If the Maximum On-Time is exceeded while responding to
a sudden increase in Load current, a normal off-time
occurs to prevent saturation of the output inductor.
Trace 1 GATE (H) (10V/div)
Trace 2 Inductor Switching Node (5V/div)
Trace 3 Output Inductor Ripple Current (2A/div)
Trace 4 VOUT ripple (20mV/div)
Figure 6: Normal Operation showing Output Inductor Ripple Current
and Output Voltage Ripple, 0.5A Load, V
OUT
= +2.825V (DAC = 10111).
Trace 1 - GATE(H) (10/div)
Trace 2 - Inductor Switching Node (5V/div)
Trace 3 - Output Inductor Ripple Current (2A/div)
Trace 4 - V
OUT
ripple (20mV/div)
Figure 7: Normal Operation showing Output Inductor Ripple Current
and Output Voltage Ripple, I
LOAD
= 14A, V
OUT
= +2.825V (DAC =
10111).
Trace 3 -Load Current (5A/10mV/div)
Trace 4 - VOUT (100mV/div)
Figure 8: Output Voltage Transient Response to a 14A load pulse,
V
OUT
= 2.825V (DAC = 10111).
Transient Response
The CS5166 V
2
TM
Control Loop’s 150ns reaction time pro-
vides unprecedented transient response to changes in
input voltage or output current. Pulse-by-pulse adjustment
of duty cycle is provided to quickly ramp the inductor cur-
rent to the required level. Since the inductor current cannot
be changed instantaneously, regulation is maintained by
the output capacitor(s) during the time required to slew
the inductor current.
Overall load transient response is further improved
through a feature called “Adaptive Voltage Positioning”.
This technique pre-positions the output capacitors voltage
to reduce total output voltage excursions during changes
in load.
Holding tolerance to 1% allows the error amplifiers refer-
ence voltage to be targeted +25mV high without compro-
mising DC accuracy. A “Droop Resistor”, implemented
through a PC board trace, connects the Error Amps feed-
9
Trace 1 - GATE(H) (10V/div)
Trace 2 - Inductor Switching Node (5V/div)
Trace 3 -Load Current (5A/div)
Trace 4 - V
OUT
(100mV/div)
Figure 9: Output Voltage Transient Response to a 14A load step, V
OUT
=
2.825V (DAC = 10111).
CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
