CS5166
Application Information: continued
where
period =
1
.
switching frequency
Trace 1 - GATE(H) (5V/div)
Trace 2 - GATE(L) (5V/div)
Figure 21: Normal Operation showing the guaranteed Non-Overlap
time between the High and Low - Side MOSFET Gate Drives, I
LOAD
=
14A.
Schottky Diode for Synchronous FET
For synchronous operation, A Schottky diode may be
placed in parallel with the synchronous FET to conduct the
inductor current upon turn off of the switching FET to
improve efficiency. The CS5166 reference circuit does not
use this device due to its excellent design. Instead, the body
diode of the synchronous FET is utilized to reduce cost and
conducts the inductor current. For a design operating at
200kHz or so, the low non-overlap time combined with
Schottky forward recovery time may make the benefits of
this device not worth the additional expense. The power
dissipation in the synchronous MOSFET due to body diode
conduction can be estimated by the following equation:
Power = V
bd
×
I
LOAD
×
conduction time
×
switching fre-
quency
Where V
bd
= the forward drop of the MOSFET body diode.
For the CS5166 demonstration board:
Power = 1.6V
×
14.2A
×
100ns
×
200kHz = 0.45W
This is only 1.1% of the 40W being delivered to the load.
“Droop” Resistor for Adaptive Voltage Positioning
Adaptive voltage positioning is used to help keep the out-
put voltage within specification during load transients. To
implement adaptive voltage positioning a “Droop
Resistor” must be connected between the output inductor
and output capacitors and load. This resistor carries the full
load current and should be chosen so that both DC and AC
tolerance limits are met. An embedded PC trace resistor
has the distinct advantage of near zero cost implementa-
tion. However, this droop resistor can vary due to three
reasons: 1) the sheet resistivity variation causes the thick-
ness of the PCB layer to vary. 2) the mismatch of L/W, and
3) temperature variation.
1) Sheet Resistivity
for one ounce copper, the thickness variation is
typically 1.15 mil to 1.35 mil. Therefore the error due to
sheet resistivity is:
1.35 - 1.15
1.25
2)
Mismatch due to L/W
= 16%
The CS5166 provides adaptive control of the external NFET
conduction times by guaranteeing a typical 65ns non-over-
lap (as seen in Figure 21) between the upper and lower
MOSFET gate drive pulses. This feature eliminates the
potentially catastrophic effect of “shoot-through current”, a
condition during which both FETs conduct causing them to
overheat, self-destruct, and possibly inflict irreversible
damage to the processor.
The most important aspect of FET performance is RDS
ON
,
which effects regulator efficiency and FET thermal man-
agement requirements.
The power dissipated by the MOSFETs may be estimated
as follows:
Switching MOSFET:
Power = I
LOAD2
×
RDS
ON
×
duty cycle
Synchronous MOSFET:
Power = I
LOAD2
×
RDS
ON
×
(1 - duty cycle)
Duty Cycle =
V
OUT
+ (I
LOAD
×
RDS
ON OF SYNCH FET
)
V
IN
+ (I
LOAD
×
RDS
ON OF SYNCH FET
) - (I
LOAD
×
RDS
ON OF SWITCH FET
)
Off Time Capacitor (C
OFF
)
The C
OFF
timing capacitor sets the regulator off time:
T
OFF
= C
OFF
×
4848.5
The preceding equation for Duty Cycle can also be used to
calculate the regulator switching frequency and select the
C
OFF
timing capacitor:
C
OFF
=
Period
×
(1-Duty Cycle)
4848.5
The variation in L/W is governed by variations due to
the PCB manufacturing process that affect the
geometry and the power dissipation capability of the
droop resistor. The error due to L/W mismatch is
typically 1%
13
CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
