CS5166
Application Information: continued
Figure 17 shows the relationship between the regulated
output voltage V
FB
and the Power-Good signal. To prevent
Power-Good from interrupting the CPU unnecessarily, the
CS5166 has a built-in delay to prevent noise at the V
FB
pin
from toggling Power-Good. The internal time delay is
designed to take about 75µs for Power-Good to go low and
65µs for it to recover. This allows the Power-Good signal to
be completely insensitive to out of regulation conditions
that are present for a duration less than the built in delay
(see Figure 18).
It is therefore required that the output voltage attains an
out of regulation or in regulation level for at least the built-
in delay time duration before the Power-Good signal can
change state.
Selecting External Components
The CS5166 buck regulator can be used with a wide range
of external power components to optimize the cost and
performance of a particular design. The following informa-
tion can be used as general guidelines to assist in their
selection.
NFET Power Transistors
Both logic level and standard FETs can be used. The refer-
ence designs derive gate drive from the 12V supply which
is generally available in most computer systems and utilize
logic level FETs. A charge pump may be easily implement-
ed to support 5V only systems. Multiple FET’s may be par-
alleled to reduce losses and improve efficiency and thermal
management.
Voltage applied to the FET gates depends on the applica-
tion circuit used. Both upper and lower gate driver outputs
are specified to drive to within 1.5V of ground when in the
low state and to within 2V of their respective bias supplies
when in the high state. In practice, the FET gates will be
driven rail to rail due to overshoot caused by the capacitive
load they present to the controller IC. For the typical appli-
cation where V
CC
= 12V and 5V is used as the source for
the regulator output current, the following gate drive is
provided:
V
GS (TOP)
= 12V - 5V = 7V, V
GS(BOTTOM)
= 12V,
(see Figure 20).
Trace 1 PWRGD (2V/div)
Trace 4 V
FB
(1V/div)
Figure 18: Power-Good is insensitive to out of regulation conditions that
are present for a duration less than the built in delay.
External Output Enable Circuit
On/off control of the regulator can be implemented
through the addition of two additional discrete compo-
nents (see Figure 19). This circuit operates by pulling the
Soft Start pin high, and the I
SENSE
pin low, emulating a cur-
rent limit condition.
5V
MMUN2111T1 (SOT-23)
Trace 3 =
GATE(H)
(10V/div.)
Trace 1=
GATE(H)
- 5V
IN
Trace 4 =
GATE(L)
(10V/div.)
Trace 2 = Inductor Switching Node (5V/div.)
5
Figure 20: Gate drive waveforms depicting rail to rail swing.
SS
CS5166
8 I
SENSE
IN4148
Shutdown
Input
Figure 19: Implementing shutdown with the CS5166.
12
CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
