Application Information: continued
Layout Guidelines
Response Time to Load Decrease
(limited by Inductor value)
When laying out the CPU buck regulator on a printed cir-
cuit board, the following checklist should be used to
ensure proper operation of the CS5165.
L × Change in IOUT
Response Time =
VOUT
1) Rapid changes in voltage across parasitic capacitors and
abrupt changes in current in parasitic inductors are major
concerns for a good layout.
Example: VOUT=+2.8V, 14.2A change in Load Current,
L = 1.2µH
2) Keep high currents out of logic grounds.
3) Avoid ground loops as they pick up noise. Use star or
single point grounding. The source of the lower (syn-
chronous FET) is an ideal point where the input and out-
put GND planes can be connected.
1.2µH × 14.2A
Response Time =
= 6.1µs
2.8V
4) For double-sided PCBs a single large ground plane is not
recommended, since there is little control of where currents
flow and the large surface area can act as an antenna.
Input and Output Capacitors
These components must be selected and placed carefully to
yield optimal results. Capacitors should be chosen to pro-
vide acceptable ripple on the input supply lines and regu-
lator output voltage. Key specifications for input capacitors
are their ripple rating, while ESR is important for output
capacitors. For best transient response, a combination of
low value/high frequency and bulk capacitors placed close
to the load will be required.
5) Even though double sided PCBs are usually sufficient
for a good layout, four-layer PCBs are the optimum
approach to reducing susceptibility to noise. Use the two
internal layers as the +5V and GND planes, and the top
and bottom layers for the vias.
6) Keep the inductor switching node small by placing the
output inductor, switching and synchronous FETs close
together.
Thermal Management
Thermal Considerations for Power MOSFETs and Diodes
7) The FET gate traces to the IC must be as short, straight,
and wide as possible. Ideally, the IC has to be placed right
next to the FETs.
In order to maintain good reliability, the junction tempera-
ture of the semiconductor components should be kept to a
maximum of 150°C or lower. The thermal impedance
(junction to ambient) required to meet this requirement can
be calculated as follows:
8) Use fewer, but larger output capacitors, keep the capaci-
tors clustered, and use multiple layer traces with heavy
copper to keep the parasitic resistance low.
T
J(MAX) - TA
Power
Thermal Impedance =
9) Place the switching FET as close to the +5V input capaci-
tors as possible.
A heatsink may be added to TO-220 components to reduce
their thermal impedance. A number of PC board layout
techniques such as thermal vias and additional copper foil
area can be used to improve the power handling capability
of surface mount components.
10) Place the output capacitors as close to the load
as possible.
11) Place the VFB filter resistor in series with the
VFB pin (pin 16) right at the pin.
EMI Management
12) Place the VFB filter capacitor right at the VFB pin (pin
16).
As a consequence of large currents being turned on and off
at high frequency, switching regulators generate noise as a
consequence of their normal operation. When designing
for compliance with EMI/EMC regulations, additional
components may be added to reduce noise emissions.
These components are not required for regulator operation
13) The “Droop” Resistor (embedded PCB trace) has to be
wide enough to carry the full load current.
14) Place the VCC bypass capacitor as close as possible to
and experimental results may allow them to be eliminated. the VCC pin.
The input filter inductor may not be required because bulk
filter and bypass capacitors, as well as other loads located
on the board will tend to reduce regulator di/dt effects on
the circuit board and input power supply. Placement of the
power component to minimize routing distance will also
help to reduce emissions.
16
CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
