CS5165
Application Information: continued
Overvoltage Protection
Overvoltage protection (OVP) is provided as result of the
normal operation of the V
2
™ control topology and requires
no additional external components. The control loop
responds to an overvoltage condition within 100ns, causing
the top MOSFET to shut off, disconnecting the regulator
from its input voltage. The bottom MOSFET is then activat-
ed, resulting in a “crowbar” action to clamp the output
voltage and prevent damage to the load (see Figures 12
and 13). The regulator will remain in this state until the
overvoltage condition ceases or the input voltage is pulled
low. The bottom FET and board trace must be properly
designed to implement the OVP function. If a dedicated
OVP output is required, it can be implemented using the
circuit in figure 14. In this figure the OVP signal will go
high (overvoltage condition), if the output voltage (V
CORE
)
exceeds 20% of the voltage set by the particular DAC code
and provided that PWRGD is low. It is also required that
the overvoltage condition be present for at least the
PWRGD delay time for the OVP signal to be activated. The
resistor values shown in figure 14 are for V
DAC
= +2.8V
(DAC = 10111). The V
OVP
(overvoltage trip-point) can be
set using the following equation:
Trace 4 = 5V from PC Power Supply (2V/div.)
Trace 1 = Regulator Output Voltage (1V/div.)
Figure 13: OVP response to an input-to-output short circuit by pulling
the input voltage to ground.
VCORE
15K
V
OVP
= V
BEQ3
(
1+
R2
R1
)
+5V
R1
Q3
2N3906
+5V
56K
5K
R2
OVP
20K
Q2
2N3904
10K
10K
10K
CS5165
Q1
PWRGD
2N3906
Figure 14: Circuit to implement a dedicated OVP output using the
CS5165.
Output Enable Circuit
The Enable pin (pin 8) is used to enable or disable the regu-
lator output voltage, and is consistent with TTL DC specifi-
cations. It is internally pulled-up. If pulled low (below
0.8V), the output voltage is disabled. At the same time the
Power Good and Soft Start pins are pulled low, so that
when normal operation resumes power-up of the CS5165
goes through the Soft Start sequence. Upon pulling the
Enable pin low, the internal IC bias is completely shut off,
resulting in total shutdown of the Controller IC.
Power Good Circuit
The Power Good pin (pin 13) is an open-collector signal
consistent with TTL DC specifications. It is externally
pulled -up, and is pulled low (below 0.3V) when the regu-
lator output voltage typically exceeds ± 8.5% of the nomi-
nal output voltage. Maximum output voltage deviation
before Power Good is pulled low is ± 12%.
Trace 4 = 5V from PC Power Supply (5V/div.)
Trace1 = Regulator Output Voltage (1V/div.)
Trace 2 = Inductor Switching Node (5V/div.)
Figure 12: OVP response to an input-to-output short circuit by immedi-
ately providing 0% duty cycle, crow-barring the input voltage to
ground.
11
CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
