CS51311
Application Information: continued
voltage, it is affected by any change in the output regard-
less of the origin of that change. The ramp signal also con-
tains the DC portion of the output voltage, which allows
the control circuit to drive the main switch to 0% or 100%
duty cycle as required.
A change in line voltage changes the current ramp in the
inductor, affecting the ramp signal, which causes the V
2
TM
control scheme to compensate the duty cycle. Since the
change in inductor current modifies the ramp signal, as in
current mode control, the V
2
TM
control scheme has the same
advantages in line transient response.
A change in load current will have an affect on the output
voltage, altering the ramp signal. A load step immediately
changes the state of the comparator output, which controls
the main switch. Load transient response is determined
only by the comparator response time and the transition
speed of the main switch. The reaction time to an output
load step has no relation to the crossover frequency of the
error signal loop, as in traditional control methods.
The error signal loop can have a low crossover frequency,
since transient response is handled by the ramp signal loop.
The main purpose of this “slow” feedback loop is to pro-
vide DC accuracy. Noise immunity is significantly
improved, since the error amplifier bandwidth can be rolled
off at a low frequency. Enhanced noise immunity improves
remote sensing of the output voltage, since the noise associ-
ated with long feedback traces can be effectively filtered.
Line and load regulation are drastically improved because
there are two independent voltage loops. A voltage mode
controller relies on a change in the error signal to compen-
sate for a deviation in either line or load voltage. This
change in the error signal causes the output voltage to
change corresponding to the gain of the error amplifier,
which is normally specified as line and load regulation.
A current mode controller maintains fixed error signal
under deviation in the line voltage, since the slope of the
ramp signal changes, but still relies on a change in the error
signal for a deviation in load. The V
2
TM
method of control
maintains a fixed error signal for both line and load varia-
tion, since the ramp signal is affected by both line and load.
Constant Off-Time
To minimize transient response, the CS51311 uses a
Constant Off-Time method to control the rate of output
pulses. During normal operation, the Off-Time of the high
side switch is terminated after a fixed period, set by the
C
OFF
capacitor. Every time the V
FB
pin exceeds the COMP
pin voltage an Off-Time is initiated. To maintain regula-
tion, the V
2
TM
Control Loop varies switch On-Time. The
PWM comparator monitors the output voltage ramp, and
terminates the switch On-Time.
Constant Off-Time provides a number of advantages.
Switch duty Cycle can be adjusted from 0 to 100% on a
pulse-by pulse basis when responding to transient condi-
tions. Both 0% and 100% Duty Cycle operation can be
maintained for extended periods of time in response to
Load or Line transients.
Programmable Output
The CS51311 is designed to provide two methods for pro-
gramming the output voltage of the power supply. A five
bit on board digital to analog converter (DAC) is used to
program the output voltage within two different ranges.
7
The first range is 2.125V to 3.525V in 100mV steps, the sec-
ond is 1.325V to 2.075V in 50mV steps, depending on the
digital input code. If all five bits are left open, the CS51311
enters adjust mode. In adjust mode, the designer can
choose any output voltage by using resistor divider feed-
back to the V
FB
pin, as in traditional controllers. The
CS51311 is specifically designed to meet or exceed Intel’s
Pentium
®
II specifications.
Error Amplifier
An inherent benefit of the V
2
TM
control topology is that
there is no large bandwidth requirement on the error
amplifier design. The reaction time to an output load step
has no relation to the crossover frequency, since transient
response is handled by the ramp signal loop. The main
purpose of this”slow”feedback loop is to provide DC accu-
racy. Noise immunity is significantly improved, since the
error amplifier bandwidth can be rolled off at a low fre-
quency. Enhanced noise immunity improves remote sens-
ing of the output voltage, since the noise associated with
long feedback traces can be effectively filtered. The COMP
pin is the output of the error amplifier and a capacitor to
Gnd compensates the error amplifier loop. Additionally,
through the built-in offset on the PWM Comparator non-
inverting input, the COMP pin provides the hiccup timing
for the Over-Current Protection, the soft start function that
minimizes inrush currents during regulator power-up and
switcher output enable.
Startup
The CS51311 provides a controlled startup of regulator
output voltage and features Programmable Soft Start
implemented through the Error Amp and external
Compensation Capacitor. This feature, combined with
overcurrent protection, prevents stress to the regulator
power components and overshoot of the output voltage
during startup.
As Power is applied to the regulator, the CS51311
Undervoltage Lockout circuit (UVL) monitors the ICs sup-
ply voltage (V
CC
) which is typically connected to the +12V
output of the AC-DC power supply. The UVL circuit pre-
vents the NFET gates from being activated until V
CC
exceeds the 8.4V (typ) threshold. Hysteresis of 300mV (typ)
is provided for noise immunity. The Error Amp Capacitor
connected to the COMP pin is charged by a 30µA current
source. This capacitor must be charged to 1.1V (typ) so that
it exceeds the PWM comparator’s offset before the V
2
TM
PWM control loop permits switching to occur.
When V
CC
has exceeded 8.4V and COMP has charged to
1.1V, the upper Gate driver (GATE(H)) is activated, turn-
ing on the upper FET. This causes current to flow through
the output inductor and into the output capacitors and
load according to the following equation:
I = (V
IN
– V
OUT
)
×
T
L
GATE(H) and the upper NFET remain on and inductor cur-
rent ramps up until the initial pulse is terminated by either
the PWM control loop or the overcurrent protection. This
initial surge of in-rush current minimizes startup time, but
avoids overstressing of the regulator’s power components.
The PWM comparator will terminate the initial pulse if the
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