欢迎访问ic37.com |
会员登录 免费注册
发布采购

CS51311 参数 Datasheet PDF下载

CS51311图片预览
型号: CS51311
PDF下载: 下载PDF文件 查看货源
内容描述: CPU同步降压控制器的12V和5V的应用 [Synchronous CPU Buck Controller for 12V and 5V Applications]
分类和应用: 控制器
文件页数/大小: 19 页 / 239 K
品牌: CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
 浏览型号CS51311的Datasheet PDF文件第2页浏览型号CS51311的Datasheet PDF文件第3页浏览型号CS51311的Datasheet PDF文件第4页浏览型号CS51311的Datasheet PDF文件第5页浏览型号CS51311的Datasheet PDF文件第7页浏览型号CS51311的Datasheet PDF文件第8页浏览型号CS51311的Datasheet PDF文件第9页浏览型号CS51311的Datasheet PDF文件第10页  
CS51311
Typical Performance Characteristics
Figure 1: Gate(H) and Gate(L) Falltime vs. Load Capacitance.
150
Figure 4: Percent Output Error vs. DAC Output
Voltage Setting, V
ID4
= 0.
0.10
Falltime (ns)
125
100
75
50
25
0
0
Output Error (%)
V
CC
= 12V
T
A
= 25°C
0.05
0
−0.05
−0.10
−0.15
2000
4000
6000
8000
10000
12000
14000
16000
V
CC
= 12V
T
A
= 25°C
V
ID4
= 0
Load Capacitance (pF)
−0.20
1.325 1.375 1.425 1.475 1.525 1.575 1.625 1.675 1.725 1.775 1.825 1.875 1.925 1.975 2.025 2.075
DAC Output Voltage Setting (V)
Figure 2: Gate(H) and Gate(L) Risetime vs. Load Capacitance.
150
Figure 5: Percent Output Error vs. DAC Output
Voltage Setting, V
ID4
= 1.
0.35
0.30
0.25
0.20
Risetime (ns)
125
100
75
50
0
25
0
V
CC
= 12V
T
A
= 25°C
Output Error (%)
0.15
0.10
0.05
0
−0.05
−0.10
2000
4000
6000
8000
10000
12000
14000
16000
Load Capacitance (pF)
Figure 3: DAC Output Voltage vs. Temperature,
DAC Code = 00001.
DAC Output Voltage
Deviation (%)
0.10
0.05
0
−0.05
−0.10
−0.15
0
20
40
60
80
100
120
−0.15
−0.20
V
CC
= 12V
T
A
= 25°C
V
ID4
= 1
−0.25
2.125 2.225 2.325 2.425 2.525 2.625 2.725 2.825 2.925 3.025 3.125 3.225 3.335 3.425 3.525
DAC Output Voltage Setting (V)
V
CC
= 12V
Junction Temperature (°C)
Application Information
Theory Of Operation
V
2
TM
Control
Method
PWM
Comparator
C
+
GATE(H)
GATE(L)
The V
2
TM
method of control uses a ramp signal that is gen-
erated by the ESR of the output capacitors. This ramp is
proportional to the AC current through the main inductor
and is offset by the value of the DC output voltage. This
control scheme inherently compensates for variation in
either line or load conditions, since the ramp signal is gen-
erated from the output voltage itself. This control scheme
differs from traditional techniques such as voltage mode,
which generates an artificial ramp, and current mode,
which generates a ramp from inductor current.
The V
2
TM
control method is illustrated in Figure 6. The out-
put voltage is used to generate both the error signal and
the ramp signal. Since the ramp signal is simply the output
6
Ramp Signal
Output
Voltage
Feedback
V
FB
Error
Amplifier
E
+
COMP
Error
Signal
Reference
Voltage
Figure 6: V
2
TM
Control Diagram