CS5106
Package Lead Description: continued
PACKAGE LEAD #
LEAD SYMBOL
FUNCTION
9
V
FB1
10
V
SS
Voltage Feedback Lead for the Auxiliary PWM. A voltage which represents
the auxiliary power supply output voltage is fed to this lead. A voltage less
than RAMP1+0.13 on V
FB1
will cause GATE1 to go low.
V
SS
power/feedback input lead. See V
CC
for description of power operation.
In addition, this lead is fed to a divide by ten resistor divider and compared to
1.2V nominal at the positive side of the error amplifier.
V
CC
power input lead. This input runs off a Zener referenced supply until
V
SS
> V
CC
. Then an internal diode which runs between V
SS
and V
CC
turns on
and all main power is derived from V
SS
.
Auxiliary PWM gate drive lead. This output normally drives the FET which
drives the auxiliary transformer.
Ground lead.
Synchronous PWM gate drive lead. This output normally drives the FET
which drives the main transformer.
Synchronous PWM gate drive lead. This output normally drives the FET for
the gate drive transformer used for synchronous rectification.
Voltage feedback lead for the synchronous PWM. A voltage which represents
the main power supply output voltage is fed to this lead. A voltage less than
RAMP2+0.13 on V
FB2
will cause GATE2 to go low and GATE2B to go high.
Current ramp input lead for the synchronous PWM. A voltage which is linear
with respect to current in the primary side of the main trans former is usually
represented on this lead. A voltage exceeding V
FB2
- 0.13 on RAMP2 will
cause GATE2 to go low and GATE2B to go high.
Pulse by pulse over current protection lead for the synchronous PWM. A volt-
age exceeding 1.2V nominal on I
LIM2
will cause GATE2 to go low and GATE2B
to go high. A voltage exceeding 1.4V nominal on I
LIM2
will cause GATE2 to go
low and GATE2B to go high for at least two clock cycles.
GATE2, GATE2B non-overlap time adjustment lead. A 27k�½ resistor from
DLYSET to ground sets the non-overlap time to 45ns nominal.
Frequency adjustment lead. A 27k�½ resistor from FADJ to ground sets the
clock frequency to 512kHz nominal.
Clock output lead. This is a 50% duty cycle, 1V to 5V pulse whose rising edge
is in phase with GATE1. This signal can be used to synchronize other power
supplies.
Clock synchronization lead. The internal clock frequency can be adjusted
+10%, -15% by the onset of positive edges of an external clock occurring on the
SYNC
IN
lead. If the external clock frequency is out side the internal clock fre-
quency by +25%, -35% the external clock is ignored and the internal clock free
runs.
ENABLE programming input. See ENABLE for programming states. PRO-
GRAM has at least 20µA min. of available source current.
PWM enable input. If PROGRAM is HIGH then a LOW on ENABLE will
allow GATE1, GATE2 and GATE2B to switch. If PROGRAM is LOW then a
HIGH on ENABLE will allow GATE1, GATE2 and GATE2B to switch. If
ENABLE is left floating, it will pull up to a HIGH level. ENABLE has at least
100µA (min) of available source current.
11
V
CC
12
13
14
15
16
GATE1
Gnd
GATE2
GATE2B
V
FB2
17
RAMP2
18
I
LIM2
19
20
21
DLYSET
FADJ
SYNC
OUT
22
SYNC
IN
23
24
PROGRAM
ENABLE
7
CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
