Theory of Application: continued
FADJ and DLYSET Leads
trollers (master). See Figure 5 for the relationship between
SYNC, CLK, and GATE waveforms.
Amplifier A2 and transistor N3 create a current source fol-
lower whose output is FADJ. An external resistor from
FADJ to ground completes the loop. The voltage across the
resistor is set by a buffered, trimmed, precision reference.
In this fashion, an accurate current is created which is used
to charge and discharge an internal capacitor thereby creat-
ing an oscillator with a tight frequency tolerance. For FADJ
resistor value selection, see Figure 3. Transistor N2 is in
parallel with N3 and is used to created an independent cur-
rent across the resistor from DLYSET to ground. This cur-
rent is used to program the GATE non-overlap delay
blocks in the main PWM drivers. For DLYSET resistor
value selection, see Figure 4.
SYNC
IN
CLK1
GATE1
CLK2
SYNC
OUT
GATE2
GATE2B
1100
1000
900
Figure 5: SYNC, GATE and CLOCK waveforms.
SYNCIN and SYNCOUT Leads
800
Multiple supplies can be synchronized to one supply by
using the SYNC leads. The SYNCIN and SYNCOUT pulses
are always 180 degrees out of phase. The SYNCIN input is
always in phase with the clock signal for the main driver
and the SYNCOUT output is always in phase with the clock
signal for the auxiliary driver. If the IC is being used as a
slave, the incoming frequency must be within +10%, -20%
of the programmed frequency set by its own FADJ resistor.
If the frequency on the SYNCIN lead is outside the internal
frequency by +25%, -35%, the SYNCIN input will be
ignored. If the SYNC signal stops while the power supplies
are in synchronized operation, the synchronized supplies
will stop and restart free running. If the SYNCIN signal
drifts out of frequency specification while the power sup-
plies are in synchronized operation, the synchronized sup-
plies will begin to free run without restarting.
700
600
500
400
300
200
100
0
60
0
10
20
30
40
Resistance kW
70
80
50
Figure 3: SYNCOUT Frequency vs. FADJ Resistors
80
70
60
Slope Compensation
DC-DC converters with current mode control require slope
compensation to avoid instability at duty cycles greater
than 50%. A slope is added to the current sense waveform
(or subtracted from the voltage waveform) that is equal to
a percentage (75% typical) of the down slope of the induc-
tor current. In the application diagram shown, the boot-
strap (flyback) transformer inductance can be chosen so
that the duty cycle never exceeds 50% and therefore does
not require slope compensation. The buck indicator in the
forward converter would typically be chosen to work in
continuous conduction mode with a maximum duty cycle
of 50-60% and would require slope compensation. Slope
compensation is accomplished as follows: R9 and C9 form
a ramp waveform rising each time GATE 2 turns on. C9 is
discharged through D3 to the same level each cycle regard-
less of duty cycle. R10 and R11 are chosen to control the
amount of slope compensation. C10 provides filtering for
noise and turn-on spikes. To calculate the required slope
compensation, calculate the buck indicator down current
and the corresponding voltage slope at the current sense
resistor - R12.
50
40
30
20
10
0
0
5
10
15
20
25
30
35
40
45
50
Resistance (kW)
Figure 4: GATE Non-Overlap Time vs. DLYSET Resistance
Oscillator
The oscillator generates two clock signals which are 180
degrees out of phase with respect to time. One clock signal
feeds the main driver and the other feeds the auxiliary
driver. Because the drivers are never turned on at the same
time, ground noise and supply noise is minimized. The
clock signals are actually 100ns pulse spikes. These spikes
create a narrow driver turn-on window. This narrow win-
dow prevents the driver from spurious turn on in the mid-
dle of a clock cycle. The oscillator can be synchronized by
an external clock (slave) or drive the clocks of other con-
The buck inductor down slope is:
A
µs
VOUT + VQ5
L1(µH)
Inductor_Slope =
(
)
10
CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
