CM6802SAH/SBH (Turbo-Speed PFC+Green PWM)
EPA/85+ ZVS-Like PFC+PWM COMBO CONTROLLER
http://www.championmicro.com.tw
Design for High Efficient Power Supply at both Full Load and Light Load
Vrms Description:
Clean Digital PFC Brown Out
VRMS pin is designed for the following functions:
Clean Digital PFC Brown Out provides a clean cut off when
AC input is much lower than regular AC input voltage such as
67Vac.
1. VRMS is used to detect the AC Brown Out (Also, we can
call it Clean Digital PFC brown out.). When VRMS is less
than 1.0 V +/-3%, PFCOUT will be turned off and VEAO
will be softly discharged. When VRMS is greater than
1.75V +/-3%, PFCOUT is enabled and VEAO is released.
Inside of Clean Digital PFC Brown Out, there is a comparator
monitors the Vrms (pin 4) voltage. Clean Digital PFC Brown
Out inhibits the PFC, and Veao (PFC error amplifier output) is
pulled down when the Vrms is lower than off threshold, 1.0V
(The off Vin voltage usually corresponds to 67.2Vac). When
the Vrms voltage reaches 1.75V (The On Vin voltage usually
corresponds to 86.6V and when Vin = 80Vac, Vrms = 1.14V),
PFC is on.
2. VRMS also is used to determine if the AC Line is high line
or it is low line. If VRMS is above 3.0V +/- 5%, IC will
recognize it is high line the. If VRMS is below 2.0V +/-
5%, it is low line. Between 2V <=~ Vrms <=~ 3.0, it is the
hysteresis.
Before PFC is turned on, Vrms (pin 4) represents the peak
voltage of the AC input. Before PFC is turned off, Vrms (pin 4)
represents the Vrms voltage of the AC input.
3. At High Line and Light Load, 380V to 342V (Vfb threshold
moves from 2.5V to 2.25V) is prohibited. At Low Line and
Light Load, 380V to 342V (Vfb threshold moves from 2.5V
to 2.25V) is enable. It provides ZVS-Like performance.
Cycle-By-Cycle Current Limiter and
Selecting RSENSE
Current Error Amplifier, IEAO
The ISENSE pin, as well as being a part of the current
feedback loop, is a direct input to the cycle-by-cycle current
limiter for the PFC section. Should the input voltage at this pin
ever be more negative than –1V, the output of the PFC will be
disabled until the protection flip-flop is reset by the clock pulse
at the start of the next PFC power cycle.
RS is the sensing resistor of the PFC boost converter. During
the steady state, line input current x RSENSE = Imul x 7.75K.
Since the maximum output voltage of the gain modulator is Imul
max x 7.75K≒ 0.8V during the steady state, RSENSE x line
The current error amplifier’s output controls the PFC duty
cycle to keep the average current through the boost inductor a
linear function of the line voltage. At the inverting input to the
current error amplifier, the output current of the gain modulator
is summed with a current which results from a negative voltage
being impressed upon the ISENSE pin. The negative voltage on
ISENSE represents the sum of all currents flowing in the PFC
circuit, and is typically derived from a current sense resistor in
series with the negative terminal of the input bridge rectifier.
input current will be limited below 0.8V as well. When VEAO
reaches maximum VEAO which is 6V, Isense can reach 0.8V.
At 100% load, VEAO should be around 4.5V and ISENSE
average peak is 0.6V. It will provide the optimal dynamic
response + tolerance of the components.
In higher power applications, two current transformers are
sometimes used, one to monitor the IF of the boost diode. As
stated above, the inverting input of the current error amplifier is
a virtual ground. Given this fact, and the arrangement of the
duty cycle modulator polarities internal to the PFC, an increase
in positive current from the gain modulator will cause the
output stage to increase its duty cycle until the voltage on
ISENSE is adequately negative to cancel this increased current.
Similarly, if the gain modulator’s output decreases, the output
duty cycle will decrease, to achieve a less negative voltage on
the ISENSE pin.
Therefore, to choose RSENSE, we use the following equation:
RSENSE + RParasitic =0.6V x Vinpeak / (2 x Line Input power)
For example, if the minimum input voltage is 80VAC, and the
maximum input rms power is 200Watt, RSENSE + RParasitic
=
(0.6V x 80V x 1.414) / (2 x 200) = 0.169 ohm. The designer
needs to consider the parasitic resistance and the margin of
the power supply and dynamic response. Assume RParasitic
0.03Ohm, RSENSE = 0.139Ohm.
=
Error Amplifier Compensation
The PWM loading of the PFC can be modeled as a negative
resistor; an increase in input voltage to the PWM causes a
decrease in the input current. This response dictates the
proper compensation of the two transconductance error
amplifiers. Figure 2 shows the types of compensation networks
most commonly used for the voltage and current error
amplifiers, along with their respective return points. The current
loop compensation is returned to VREF to produce a soft-start
characteristic on the PFC: as the reference voltage comes up
from zero volts, it creates a differentiated voltage on IEAO which
prevents the PFC from immediately demanding a full duty
cycle on its boost converter.
PFC OVP
In the CM6802SAH/SBH, PFC OVP comparator serves to
protect the power circuit from being subjected to excessive
voltages if the load should suddenly change. A resistor divider
from the high voltage DC output of the PFC is fed to VFB.
When the voltage on VFB exceeds ~ 2.85V, the PFC output
driver is shut down. The PWM section will continue to operate.
The OVP comparator has 250mV of hysteresis, and the PFC
will not restart until the voltage at VFB drops below ~ 2.55V.
The VFB power components and the CM6802SAH/SBH are
within their safe operating voltages, but not so low as to
interfere with the boost voltage regulation loop.
2009/11/02 Rev. 1.5
Champion Microelectronic Corporation
16
CHAMP [ CHAMPION MICROELECTRONIC CORP. ]
