CM6802SAH/SBH (Turbo-Speed PFC+Green PWM)
EPA/85+ ZVS-Like PFC+PWM COMBO CONTROLLER
http://www.championmicro.com.tw
Design for High Efficient Power Supply at both Full Load and Light Load
Dynamic Soft PFC (patent pending)
Gain=Imul/Iac
Besides all the goodies from CM6800A, Dynamic Soft PFC
is the main feature of CM6802SAH/SBH. Dynamic Soft PFC is
to improve the efficiency, to reduce power device stress, to
ease EMI, and to ease the monotonic output design while it
has the more protection such as the short circuit with
power-foldback protection. Its unique sequential control
maximizes the performance and the protections among steady
state, transient and the power on/off conditions.
K=Gain/(VEAO-0.7V)
I
mul = K x (VEAO – 0.7V) x IAC
Where K is in units of [V-1]
Note that the output current of the gain modulator is limited
around 100 μA and the maximum output voltage of the gain
modulator is limited to 100uA x 7.75K≒0.8V. This 0.8V also
PFC Section:
will determine the maximum input power.
Gain Modulator
However, IGAINMOD cannot be measured directly from ISENSE
.
Figure 1 shows a block diagram of the PFC section of the
CM6802SAH/SBH. The gain modulator is the heart of the PFC,
as it is this circuit block which controls the response of the
current loop to line voltage waveform and frequency, rms line
voltage, and PFC output voltages. There are three inputs to
the gain modulator. These are:
ISENSE = IGAINMOD-IOFFSET and IOFFSET can only be measured
when VEAO is less than 0.5V and IGAINMOD is 0A. Typical
IOFFSET is around 25uA.
IAC=20uA, Veao=6V
1. A current representing the instantaneous input voltage
(amplitude and wave-shape) to the PFC. The rectified AC
input sine wave is converted to a proportional current via a
resistor and is then fed into the gain modulator at IAC
.
Sampling current in this way minimizes ground noise, as is
required in high power switching power conversion
environments. The gain modulator responds linearly to this
current.
2. A voltage proportional to the long-term RMS AC line voltage,
derived from the rectified line voltage after scaling and
filtering. This signal is presented to the gain modulator at
VRMS. The gain modulator’s output is inversely proportional
to VRMS2. The relationship between VRMS and gain is
illustrated in the Typical Performance Characteristics of this
page.
Gain vs. VRMS (pin4)
3. The output of the voltage error amplifier, VEAO. The gain
modulator responds linearly to variations in this voltage.
When VRMS below 1V, the PFC is shut off. Designer needs
to design 80VAC with VRMS average voltage= 1.14V.
The output of the gain modulator is a current signal, in the
form of a full wave rectified sinusoid at twice the line
frequency. This current is applied to the virtual-ground
(negative) input of the current error amplifier. In this way the
gain modulator forms the reference for the current error loop,
and ultimately controls the instantaneous current draw of the
PFC from the power line. The general formula of the output of
the gain modulator is:
ISENSE − IOFFSET IMUL
Gain =
=
IAC
IAC
Selecting RAC for IAC pin
IAC pin is the input of the gain modulator. IAC also is a
current mirror input and it requires current input. By selecting a
proper resistor RAC, it will provide a good sine wave current
derived from the line voltage and it also helps program the
maximum input power and minimum input line voltage.
I
AC× (VEAO -0.7V)
Imul
=
x constant
(1)
2
V
RMS
RAC=Vin min peak x 53.03K. For example, if the minimum line
voltage is 80VAC, the RAC=80 x 1.414 x 53.03K = 6 Mega ohm.
2009/11/02 Rev. 1.5
Champion Microelectronic Corporation
15
CHAMP [ CHAMPION MICROELECTRONIC CORP. ]
