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CAT28C64BG-12T 参数 Datasheet PDF下载

CAT28C64BG-12T图片预览
型号: CAT28C64BG-12T
PDF下载: 下载PDF文件 查看货源
内容描述: 64K位CMOS并行EEPROM [64K-Bit CMOS PARALLEL EEPROM]
分类和应用: 内存集成电路可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件页数/大小: 13 页 / 415 K
品牌: CATALYST [ CATALYST SEMICONDUCTOR ]
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CAT28C64B  
Page Write  
(which can be loaded in any order) during the first and  
subsequent write cycles. Each successive byte load  
cycle must begin within tBLC MAX of the rising edge of the  
preceding WE pulse. There is no page write window  
The page write mode of the CAT28C64B (essentially an  
extended BYTE WRITE mode) allows from 1 to 32 bytes  
ofdatatobeprogrammedwithinasingleEEPROMwrite  
cycle. This effectively reduces the byte-write time by a  
factor of 32.  
limitation as long as WE is pulsed low within tBLC MAX  
.
Upon completion of the page write sequence, WE must  
stay high a minimum of tBLC MAX for the internal auto-  
matic program cycle to commence. This programming  
cycle consists of an erase cycle, which erases any data  
that existed in each addressed cell, and a write cycle,  
whichwritesnewdatabackintothecell. Apagewritewill  
only write data to the locations that were addressed and  
will not rewrite the entire page.  
FollowinganinitialWRITEoperation(WEpulsedlow,for  
tWP, and then high) the page write mode can begin by  
issuing sequential WE pulses, which load the address  
anddatabytesintoa32bytetemporarybuffer. Thepage  
address where data is to be written, specified by bits A5  
to A12, is latched on the last falling edge of WE. Each  
byte within the page is defined by address bits A0 to A4  
Figure 5. Byte Write Cycle [CE Controlled]  
t
WC  
ADDRESS  
t
t
t
BLC  
AS  
AH  
t
CW  
CE  
OE  
WE  
t
OEH  
t
OES  
t
t
CH  
CS  
HIGH-Z  
DATA OUT  
DATA IN  
DATA VALID  
DS  
t
t
DH  
Figure 6. Page Mode Write Cycle  
OE  
CE  
WE  
t
t
BLC  
WP  
ADDRESS  
I/O  
t
WC  
LAST BYTE  
BYTE n+2  
BYTE 0 BYTE 1  
BYTE 2  
8
BYTE n  
BYTE n+1  
Doc. No. 1011, Rev. F