PRELIMINARY
CM3202-02
Package Pinout
PACKAGE / PINOUT DIAGRAM
Top View
(Pins Down View)
Pin 1
Marking
Top View
Thermal Pad
VIN
VIN
VTT
GND
(Pins Down View)
VIN
NC
VTT
NC
1
8
VDDQ
ADJSD
GND
GND
1
8
VDDQ
VDDQ
ADJSD
GND
CM3202
02SM
CM320
202DE
2
3
4
7
6
5
2
3
4
7
6
5
8-Lead TDFN Package
CM3202-02DE
Note: These drawings are not to scale.
8-Lead SOIC Package
CM3202-02SM
PIN DESCRIPTIONS
PIN(s)
TDFN-8
1
2
3
4
5
6
7
5
4
6
3
PIN(s)
SOIC-8
1,2
NAME
VIN
NC
VTT
NC
GND
GND
ADJSD
DESCRIPTION
Input supply voltage pin. Bypass with a 220μF capacitor to GND.
Not internally connected. For better heat flow, connect to GND (exposed pad).
VTT regulator output pin, which is preset to 50% of V
DDQ
.
Not internally connected. For better heat flow, connect to GND (exposed pad).
Ground pin (analog).
Ground pin (power).
This pin is for V
DDQ
output voltage adjustment. It is available as long as V
DDQ
is
enabled. During Manual/Thermal shutdown, it is tightened to GND. The V
DDQ
output
voltage is set using an external resistor divider connected to ADJSD:
R1
+
R2
-
V
DDQ
= 1.25V
×
--------------------
R2
where R1 is the upper resistor and R2 is the ground-side resistor. In addition, the
ADJSD pin functions as a Shutdown pin. When ADJSD voltage is higher than 2.7V
(SHDN_H), the circuit is in Shutdown mode. When ADJSD voltage is below 1.5V
(SHDN_L), both VDDQ and VTT are enabled. A low-leakage Schottky diode in series
with ADJSD pin is recommended to avoid interference with the voltage adjustment
setting.
8
EPad
7,8
VDDQ
GND
VDDQ regulator output voltage pin.
The backside exposed pad which serves as the package heatsink. Must be
connected to GND.
© 2007 California Micro Devices Corp. All rights reserved.
2
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
●
Tel: 408.263.3214
●
Fax: 408.263.7846
●
www.cmd.com
05/25/07
CALMIRCO [ CALIFORNIA MICRO DEVICES CORP ]
