PRELIMINARY
CM3202-02
Application Info
Powering DDR Memory
The VTT power requirement is proportional to the
number of data lines and the resistance of the
termination resistor, but does not vary with memory
size. In a typical DDR data bus system each data line
termination may momentarily consume 16.2mA to
Double-Data-Rate (DDR) memory has provided a huge
step in performance for personal computers, servers
and graphic systems. As is apparent in its name, DDR
operates at double the data rate of earlier RAM, with
two memory accesses per cycle versus one. DDR
SDRAMs transmit data at both the rising and falling
edges of the memory bus clock.
achieve the 405mV minimum over V needed at the
TT
receiver:
405mV
Iterminaton = -------------------- = 16.2mA
Rt(25Ω)
DDR’s use of Stub Series Terminated Logic (SSTL)
topology improves noise immunity and power-supply
rejection, while reducing power dissipation. To achieve
this performance improvement, DDR requires more
complex power management architecture than
previous RAM technology.
A typical 64Mbyte SSTL-2 memory system, with 128
terminated lines, has a worst-case maximum V
TT
supply current up to 2.07A. However, a DDR memory
system is dynamic, and the theoretical peak currents
only occur for short durations, if they ever occur at all.
Unlike the conventional DRAM technology, DDR
SDRAM uses differential inputs and a reference
voltage for all interface signals. This increases the data
bus bandwidth, and lowers the system power
consumption. Power consumption is reduced by lower
operating voltage, a lower signal voltage swing
associated with Stub Series Terminated Logic
These high current peaks can be handled by the V
TT
external capacitor. In a real memory system, the
continuous average V current level in normal
TT
operation is less than 200mA.
The VDDQ power supply, in addition to supplying
current to the memory banks, could also supply current
to controllers and other circuitry. The current level
typically stays within a range of 0.5A to 1A, with peaks
up to 2A or more, depending on memory size and the
computing operations being performed.
(SSTL_2), and by the use of a termination voltage, V .
TT
SSTL_2 is an industry standard defined in JEDEC
document JESD8-9. SSTL_2 maintains high-speed
data bus signal integrity by reducing transmission
reflections. JEDEC further defines the DDR SDRAM
specification in JESD79C.
The tight tracking requirements and the need for V to
TT
sink, as well as source, current provide unique
challenges for powering DDR SDRAM.
DDR memory requires three tightly regulated voltages:
V
, V , and V
(see Figure 1). In a typical
DDQ
TT
REF
CM3202-02 Regulator
SSTL_2 receiver, the higher current V
supply
DDQ
The CM3202-02 dual output linear regulator provides
all of the power requirements of DDR memory by
combining two linear regulators into a single TDFN-8
package. VDDQ regulator can supply up to 2A current,
voltage is normally 2.5V with a tolerance of 200mV.
The active bus termination voltage, V , is half of
TT
V
V
. V
is a reference voltage that tracks half of
REF
DDQ
1%, and is compared with the V terminated
DDQ
TT
and the two-quadrant V
termination regulator has
TT
signal at the receiver. V must be within 40-mV of
TT
current sink and source capability to 2A. The VDDQ
linear regulator uses a PMOS pass element for a very
low dropout voltage, typically 500mV at a 2A output.
V
.
REF
VDDQ
VTT (=VDDQ/2) VDDQ
Rt = 25
The output voltage of V
can be set by an external
DDQ
voltage divider. The use of regulators for both the
upper and lower side of the VDDQ output allows a fast
transient response to any change of the load, from high
current to low current or inversely. The second output,
Line
Rs = 25
Transmitter
Receiver
V , is regulated at V
/2 by an internal resistor
TT
DDQ
divider. Same as VDDQ, VTT has the same fast
transient response to load change in both directions.
VREF (=VDDQ/2)
The V regulator can source, as well as sink, up to 2A
TT
Figure 1. Typical DDR terminations, Class II
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www.cmd.com 05/25/07
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