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TMC2242B 参数 Datasheet PDF下载

TMC2242B图片预览
型号: TMC2242B
PDF下载: 下载PDF文件 查看货源
内容描述: 数字半带插值/抽取滤波器的12位输入/ 16位输出, 60 MHz的 [Digital Half-Band Interpolating/Decimating Filter 12-bit In/16-bit Out, 60 MHz]
分类和应用:
文件页数/大小: 16 页 / 188 K
品牌: CADEKA [ CADEKA MICROCIRCUITS LLC. ]
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TMC2242A/TMC2242B  
PRODUCT SPECIFICATION  
Pin Descriptions  
Pin Number  
PLCC MQFP  
Timing Controls  
Pin Name  
Pin Function Description  
INT  
44  
38  
Interpolate. When INT is LOW and DEC is HIGH, the input data register runs at  
1/2 the CLK rate and zeros are inserted in the data stream between valid input  
values, reducing gain by 6dB. The TMC2242A and TMC2242B interpolate and  
output results at the full CLK rate.  
DEC  
1
39  
Decimate. When DEC is LOW and INT is HIGH, the input data register runs at  
the full CLK rate. In this mode, the TMC2242A and TMC2242B decimate and  
output results at 1/2 the CLK rate.  
When INT = DEC, the TMC2242A is in equal rate mode. When both INT and DEC  
are HIGH, the TMC2242B is likewise in equal-rate mode, but when both INT and  
DEC are LOW, the TMC2242B interpolates with unity gain.  
In equal-rate mode, the input and output sample rates equal the chip clock rate.  
SYNC  
43  
42  
37  
36  
Synchronization. Incoming data are synchronized by holding SYNC HIGH on  
CLK N–1 and LOW on CLK N when the first input data word is present on SI  
.
11-0  
If DEC = INT=1 (equal rate mode), SYNC is inactive. SYNC may be held LOW  
until resynchronization is desired, or it may be toggled at 1/2 the CLK rate.  
CLK  
Clock. The TMC2242A and TMC2242B operate from a single master clock. All  
internal registers, except the output register in decimation mode, are strobed on  
the rising edge of CLK. All timing parameters are referenced to the rising edge of  
CLK.  
Data Inputs  
SI  
11-0  
40,  
34,  
Input Data Port. A 12-bit 2's-complement input word is registered by the rising  
37-30, 31-24, edge of CLK. In Interpolate Mode, SI  
is registered on every other CLK  
11-0  
27-25 21-19 (synchronized by SYNC). SI is the MSB.  
11  
Data Outputs  
SO  
4-11,  
42-44, Output Data Port. A 16-bit 2's-complement output result is available after the  
15-0  
14-21 1-5,  
8-15  
rising edge of CLK. In Decimate Mode, SO is registered on every other CLK  
15-0  
(synchronized by SYNC). SO  
15-0  
is rounded according to the state of RND .  
2-0  
SO is the MSB.  
15  
The limiter circuitry ensures that for internal overflow, a valid full-scale output  
(7FFF or 8000) will be generated. With the TMC2242B in interpolate mode with  
-6dB gain, limits are 3FFF and C000 (TCO=1).  
Output Controls  
OE  
3
41  
40  
Output Enable. When LOW, SO  
15-0  
high-impedance state. OE is asynchronous with respect to CLK.  
are enabled. When HIGH, SO are in a  
15-0  
TCO  
RND  
2
Output Format. When TCO is HIGH, output data are in signed 2's-complement  
format. When LOW, the output is inverted offset binary.  
22-24 16-18 Rounding Select. These inputs set the position of the effective LSB of the output  
2-0  
result. Outputs below the rounding bit are zeroed (Table 4).  
Power  
V
DD  
13,29, 7, 23, Supply Voltage. +5 Volt power inputs. These should come from the same power  
38  
32  
source and be decoupled to GND.  
GND  
12,28, 6, 22, Ground. Ground inputs should be connected to the system digital ground plane.  
39,41 33, 35  
3